SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 129
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SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
Entry into debug state on breakpoint
The ARM7TDMI core marks instructions as being breakpointed as they enter the
instruction pipeline, but the core does not enter debug state until the instruction reaches
the Execute stage.
Breakpointed instructions are not executed. Instead, the processor enters debug state.
When you examine the internal state, you see the state before the breakpointed
instruction. When your examination is complete, remove the breakpoint. This is usually
handled automatically by the debugger which also restarts program execution from the
previously-breakpointed instruction.
When a breakpointed conditional instruction reaches the Execute stage of the pipeline,
the breakpoint is always taken.
The processor enters debug state regardless of whether the condition is met.
A breakpointed instruction does not cause the ARM7TDMI core to enter debug state
when:
•
BREAKPT
A branch or a write to the PC precedes the breakpointed instruction. In this case,
when the branch is executed, the core flushes the instruction pipeline and so
cancels the breakpoint.
DBGACK
Note
nMREQ
D[31:0]
A[31:0]
MCLK
SEQ
Copyright © 1994-2001. All rights reserved.
Memory cycles
Figure 5-3 Debug state entry
Internal cycles
Debug Interface
5-7
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