SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 92

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
3-22
ARM7TDMI core test chip example system
Connecting the ARM7TDMI processor data bus, D[31:0] to an external shared bus
requires additional logic that varies between applications in the case of a test chip.
In this application, care must be taken to prevent bus clash on D[31:0] when the data
bus drive changes direction. The timing of nENIN, and the pad control signals must be
arranged so that when the core starts to drive out, the pad drive onto D[31:0] is disabled
before the core starts to drive. Similarly, when the bus switches back to input, the core
must stop driving before the pad is enabled.
The circuit implemented in the ARM7TDMI processor test chip is shown in Figure 3-17
on page 3-23.
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ARM DDI 0029G