SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 56
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SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.6.2
2-10
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
The Thumb-state register set
= banked register
CPSR
The Thumb-state register set is a subset of the ARM-state set. The programmer has
access to:
•
•
•
•
•
There are banked SPs, LRs, and SPSRs for each privileged mode. This register set is
shown in Figure 2-4.
SPSR_fiq
r0
r1
r2
r3
r4
r5
r6
r7
SP_fiq
LR_fiq
PC
Thumb-state general registers and program counter
CPSR
FIQ
8 general registers, r0–r7
the PC
the SP
the LR
the CPSR.
Thumb-state program status registers
Copyright © 1994-2001. All rights reserved.
Supervisor
SPSR_svc
r0
r1
r2
r3
r4
r5
r6
r7
SP_svc
LR_svc
PC
CPSR
Figure 2-4 Register organization in Thumb state
SPSR_abt
r0
r1
r2
r3
r4
r5
r6
r7
SP_abt
LR_abt
PC
CPSR
Abort
SPSR_irq
r0
r1
r2
r3
r4
r5
r6
r7
SP_irq
LR_irq
PC
CPSR
IRQ
ARM DDI 0029G
Undefined
SPSR_und
r0
r1
r2
r3
r4
r5
r6
r7
SP_und
LR_und
PC
CPSR
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