SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 81
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SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.4
3.4.1
3.4.2
3.4.3
ARM DDI 0029G
Addressing signals
A[31:0]
nRW
MAS[1:0]
The address class signals are:
•
•
•
•
•
•
•
A[31:0] is the 32-bit address bus that specifies the address for the transfer. All addresses
are byte addresses, so a burst of word accesses results in the address bus incrementing
by four for each cycle.
The address bus provides 4GB of linear addressing space.
When a word access is signaled the memory system ignores the bottom two bits, A[1:0],
and when a halfword access is signaled the memory system ignores the bottom bit,
A[0].
All data values must be aligned on their natural boundaries. All words must be
word-aligned.
nRW specifies the direction of the transfer. nRW indicates an ARM7TDMI processor
write cycle when HIGH, and an ARM7TDMI processor read cycle when LOW. A burst
of S-cycles is always either a read burst, or a write burst. The direction cannot be
changed in the middle of a burst.
The MAS[1:0] bus encodes the size of the transfer. The ARM7TDMI processor can
transfer word, halfword, and byte quantities.
All writable memory in an ARM7TDMI processor based system must support the
writing of individual bytes or halfwords to allow the use of the C Compiler and the
ARM debug tool chain, for example Multi-ICE.
A[31:0] on page 3-11
nRW on page 3-11
MAS[1:0] on page 3-11
nOPC on page 3-12
nTRANS on page 3-13
LOCK on page 3-13
TBIT on page 3-13.
Copyright © 1994-2001. All rights reserved.
Memory Interface
3-11
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