SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 67
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SAM9M11
Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Specifications of SAM9M11
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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2.8.7
2.8.8
2.8.9
ARM DDI 0029G
Software interrupt instruction
Undefined instruction
Exception vectors
Address
The Software Interrupt instruction (SWI) is used to enter Supervisor mode, usually to
request a particular supervisor function. The SWI handler reads the opcode to extract
the SWI function number.
A SWI handler returns by executing the following irrespective of the processor
operating state:
This action restores the PC and CPSR, and returns to the instruction following the SWI.
When the ARM7TDMI processor encounters an instruction that neither it, nor any
coprocessor in the system can handle, the ARM7TDMI core takes the undefined
instruction trap. Software can use this mechanism to extend the ARM instruction set by
emulating undefined coprocessor instructions.
After emulating the failed instruction, the trap handler executes the following
irrespective of the processor operating state:
This action restores the CPSR and returns to the next instruction after the undefined
instruction.
For more information about undefined instructions, see the ARM Architecture Reference
Manual.
Table 2-4 lists the exception vector addresses. In this table, I and F represent the
previous value of the IRQ and FIQ interrupt disable bits respectively in the CPSR.
Exception
Reset
Undefined instruction
Software interrupt
Prefetch Abort
Copyright © 1994-2001. All rights reserved.
Mode on entry
Supervisor
Undefined
Supervisor
Abort
I state on entry
Set
Set
Set
Set
Table 2-4 Exception vectors
Programmer’s Model
F state on entry
Set
Unchanged
Unchanged
Unchanged
2-21
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