SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 206

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.28
8-46
Cycle
coproces
sor
absent in
decode
coproces
sor
absent in
execute
a. IREQ = InMREQ, ISEQ.
b. DREQ = DnMREQ, DSEQ.
c. P = PASS.
d. LC = LATECANCEL.
Coprocessor absent
1
2
3
4
1
.
n
n+1
n+2
n+3
IA
pc+3i
0x4
0x8
0xC
pc+3i
pc+3i
pc+3i
0x4
0x8
0xC
If no coprocessor is able to process a coprocessor instruction, the instruction is treated
as an UNDEFINED instruction. This allows software to emulate coprocessor
instructions when no hardware coprocessor is present.
By default, CHSD and CHSE must be driven to ABSENT unless the coprocessor
instruction is being handled by a coprocessor. Coprocessor operations are only available
in ARM state.
The cycle timings for coprocessor absent instructions are shown in Table 8-35.
IREQ
I cycle
N cycle
S cycle
S cycle
I cycle
I cycle
I cycle
N cycle
S cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
a
INST
R
(pc+2i)
-
(0x4)
(0x8)
(0xC)
(pc+2i)
-
-
-
(0x4)
(0x8)
(0xC)
DA
-
-
-
-
-
-
-
-
-
-
Table 8-35 Coprocessor absent instruction cycle timing
DREQ
I cycle
I cycle
I cycle
I cycle
I cycle
I cycle
I cycle
I cycle
I cycle
I cycle
b
RDATA/
WDATA
-
-
-
-
-
-
-
-
-
-
P
1
0
0
0
1
0
0
0
0
0
c
LC
0
0
0
0
0
0
0
0
0
0
d
CHSD
ABSENT
-
-
WAIT
ARM DDI 0165B
CHSE
-
-
-
-
WAIT
WAIT
ABSENT
-