SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 274

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C.10.5 Debug control register
C-34
The debug control register is 6 bits wide. Writing control bits occurs during a register
write access (with the read/write bit HIGH). Reading control bits occurs during a
register read access (with the read/write bit LOW).
Figure C-10 shows the function of each bit in this register.
These functions are described in Table C-7 and Table C-8 on page C-35.
Bit
number
5
4
3
2
1:0
Embedded-ICE
disable
5
Copyright © 2000 ARM Limited. All rights reserved.
Name
Embedded-
ICE disable
Monitor
mode
enable
Single-step
INTDIS
DBGRQ,
DBGACK
Monitor mode
enable
4
Function
Controls the address and data comparison logic contained within
the Embedded-ICE logic. When set to 1, the address and data
comparators are disabled. When set to 0, the address and data
comparators are enabled. You can use this bit to save power in a
system where the Embedded-ICE functionality is not required.
The reset state of this bit is 0 (comparators enabled). An extra
piece of logic initialized by debug reset ensures that the
Embedded-ICE logic is automatically disabled out of reset. This
extra logic is set by debug reset and is automatically reset on the
first access to scan chain 2.
Controls the selection between monitor mode debug (monitor
mode enable = 1) and halt mode debug. In monitor mode,
breakpoints and watchpoints cause Prefetch Aborts and Data
Aborts to be taken (respectively). At reset, the monitor mode
enable bit is set to 1.
Controls the single-step hardware. This is explained in more
detail in Single-stepping on page C-40.
If bit 2 (INTDIS) is asserted, the interrupt signals to the
processor are inhibited. Table C-8 shows interrupt signal control.
These bits allow the values on DBGRQ and DBGACK to be
forced.
Single-step
3
Table C-7 Debug control register bit functions
Figure C-10 Debug control register format
INTDIS
2
DBGRQ
1
ARM DDI 0165B
DBGACK
0