SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 75
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 75 of 290
- Download datasheet (5Mb)
3.3
ARM DDI 0165B
ARM9E-S behavior on exit from reset
INSTR[31:0]
DnMREQ
nRESET
DA[31:0]
InMREQ
DMORE
IA[31:1]
DnRW
DSEQ
ISEQ
CLK
When nRESET is driven LOW, the currently executing instruction terminates
abnormally. InMREQ, ISEQ, DnMREQ, DSEQ, and DMORE change
asynchronously to indicate an internal cycle. When nRESET is driven HIGH, the
ARM9E-S starts requesting instructions from memory again once the nRESET signal
has been registered, and the first memory access starts two cycles later. The nRESET
signal is sampled on the rising-edge of CLK.
The behavior of the memory interface coming out of reset is shown in Figure 3-2.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 3-2 ARM9E-S behavior on exit from reset
Device Reset
3-5
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