SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 280

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C.12
C-40
Single-stepping
The ARM9E-S EmbeddedICE-RT logic contains logic that allows efficient
single-stepping through code. This leaves the watchpoint comparators free for general
use.
Enable this function by setting bit 3 of the debug control register. The state of this bit
must only be altered while the processor is in debug state. If the processor exits debug
state and this bit is HIGH, the processor fetches an instruction, executes it, and then
immediately reenters debug state. This happens independently of the watchpoint
comparators. If a system speed data access is performed while in debug state, the
debugger must ensure that the control bit is clear first.
This bit must not be set when using monitor mode debug.
Note
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B