SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 80

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.3
4.3.1
4.3.2
4-4
Instruction interface addressing signals
IA[31:1]
ITBIT
The address class signals for the instruction memory interface are:
•
•
•
•
IA[31:1] is the 31-bit address bus that specifies the address for the transfer. All
addresses are byte addresses, so a burst of 32-bit instruction fetches results in the
address bus incrementing by four for each cycle.
The ARM9E-S does not produce IA[0] as all instruction accesses are halfword-aligned
(that is, IA[0] = 0).
The address bus provides 4GB of linear addressing space. When a word access is
signaled the memory system must ignore IA[1].
The ITBIT signal encodes the size of the instruction fetch. The ARM9E-S can request
word-sized instructions (when in ARM state) or halfword-sized instructions (when in
Thumb state). This is encoded on ITBIT as shown in Table 4-1.
The size of transfer does not change during a burst of S cycles.
IA[31:1]
ITBIT
InTRANS on page 4-5
InM[4:0] on page 4-5.
Note
Copyright © 2000 ARM Limited. All rights reserved.
ITBIT
1
0
Table 4-1 Transfer widths
Transfer width
Halfword
Word
ARM DDI 0165B