SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 262

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C-22
INSTR[31:0]
DBGACK
InMREQ
IA[31:1]
ISEQ
CLK
For example, consider a peripheral that simply counts the number of instruction fetches.
This device must return the same answer after a program has run both with and without
debugging.
Figure C-5 shows the behavior of the ARM9E-S on exit from debug state.
In Figure C-6 on page C-23, you can see that two instructions are fetched after the
instruction which breakpoints. Figure C-5 shows that DBGACK masks the first three
instruction fetches out of the debug state, corresponding to the breakpoint instruction,
and the two instructions prefetched after it.
Under some circumstances DBGACK can remain HIGH for more than three
instruction fetches. Therefore, if you require precise instruction access counting, you
must provide some external logic to generate a modified DBGACK that always falls
after three instruction fetches.
When system speed accesses occur, DBGACK remains HIGH throughout. It then falls
after the system speed memory accesses are completed, and finally rises again as the
processor reenters debug state. Therefore, DBGACK masks all system speed memory
accesses.
Internal Cycles
Note
Copyright © 2000 ARM Limited. All rights reserved.
IAb
N
IAb+4
S
IAb+8
S
Figure C-5 Debug exit sequence
ARM DDI 0165B