SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 110
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SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 110 of 290
- Download datasheet (5Mb)
Interrupts
5.1
5-2
About interrupts
The ARM9E-S provides a two-level, fixed-priority asynchronous hardware interrupt
scheme. Asynchronous is used here to mean asynchronous to the instruction flow, not
to the processor clock (CLK). Refer to Chapter 9 AC Parameters for details on interrupt
signal timing.
The Fast Interrupt Request (FIQ) exception provides support for fast interrupts. The
Interrupt Request (IRQ) exception provides support for normal priority interrupts.
Refer to Exceptions on page 2-20 for more details about the programmer’s model for
interrupts.
This chapter discusses:
•
•
•
issues concerning the hardware interface to the ARM9E-S interrupt mechanism
that a system designer must be aware of when integrating an ARM9E-S system
issues that a programmer must be aware of when writing interrupt handler
routines
the worst case and best case interrupt latency.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
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