SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 225
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
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- Download datasheet (5Mb)
ARM DDI 0165B
Name
DnM[4:0]
Data mode
DnRW
Data not read, write
DnSPEC
Not data speculative
request
DnTRANS
Data not memory translate
DSEQ
Data sequential address
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Output
Output
Output
Output
Table A-3 Data memory interface signals (continued)
Description
The processor mode that any data memory
accesses must be performed in. Valid with the
data address.
If LOW at the end of the cycle, then any data
memory access in the following cycle is a read.
If HIGH then it is a write.
If LOW at the end of the cycle, then the
processor is indicating to the memory system
that the data stored at the memory location
specified by DA might be required in
subsequent cycles. DnSPEC is a speculative
signal, so the memory system does not have to
perform any action based on DnSPEC unless it
sees fit. The memory system must return an
abort for a speculative access. DnSPEC is not
asserted in the same cycle as DnMREQ.
If LOW at the end of a cycle, then any data
memory access must be performed with User
mode privileges. If HIGH it must have
Supervisor mode privileges.
If HIGH at the end of the cycle, then any data
memory access in the following cycle is
sequential from the last data memory access.
Signal Descriptions
A-5
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