SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 245
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 245 of 290
- Download datasheet (5Mb)
C.2
ARM DDI 0165B
Resetting the TAP controller
The boundary-scan interface includes a state machine controller called the TAP
controller. To force the TAP controller into the correct state after power-up, you must
apply a reset pulse to the DBGnTRST signal:
•
•
A clock on CLK with DBGTCKEN HIGH is not necessary to reset the device.
The action of reset is as follows:
1.
2.
System mode is selected. This means that the boundary-scan cells do not intercept
to ready the boundary-scan interface for use, drive DBGnTRST LOW, and then
HIGH again
to prevent the boundary-scan interface from being used, the DBGnTRST input
can be tied permanently LOW.
any of the signals passing between the external system and the core.
The IDCODE instruction is selected. When the TAP controller is put into the
SHIFT-DR state, and CLK is pulsed while enabled by DBGTCKEN, the
contents of the ID register are clocked out of DBGTDO.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Debug in depth
C-5
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