SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 140
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 140 of 290
- Download datasheet (5Mb)
Debug Interface and EmbeddedICE-RT
7.1
7.1.1
7.1.2
7-2
About the debug interface
Halt mode
Monitor mode
The ARM9E-S debug interface is based on IEEE Std. 1149.1-1990, Standard Test
Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation
of the terms used in this chapter and for a description of the TAP controller states.
The ARM9E-S contains hardware extensions for advanced debugging features. These
make it easier to develop application software, operating systems, and the hardware
itself. ARM9E-S supports two modes of debug operation:
•
•
In halt mode debug, the debug extensions allow the core to be forced into debug state.
In debug state, the core is stopped and isolated from the rest of the system. This allows
the internal state of the core, and the external state of the system, to be examined while
all other system activity continues as normal. When debug has been completed, the core
and system state can be restored, and program execution resumed.
On a breakpoint or watchpoint, an Instruction Abort or Data Abort is generated instead
of entering halt mode debug. When used in conjunction with a debug monitor program
activated by the abort exception entry, it is possible to debug the ARM9E-S while
allowing the execution of critical interrupt service routines. The debug monitor program
typically communicates with the debug host over the ARM9E-S debug communication
channel. Monitor mode debug is described in Monitor mode debug on page 7-21.
Halt mode
Monitor mode.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
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