SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 262
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 262 of 290
- Download datasheet (5Mb)
Debug in depth
C-22
INSTR[31:0]
DBGACK
InMREQ
IA[31:1]
ISEQ
CLK
For example, consider a peripheral that simply counts the number of instruction fetches.
This device must return the same answer after a program has run both with and without
debugging.
Figure C-5 shows the behavior of the ARM9E-S on exit from debug state.
In Figure C-6 on page C-23, you can see that two instructions are fetched after the
instruction which breakpoints. Figure C-5 shows that DBGACK masks the first three
instruction fetches out of the debug state, corresponding to the breakpoint instruction,
and the two instructions prefetched after it.
Under some circumstances DBGACK can remain HIGH for more than three
instruction fetches. Therefore, if you require precise instruction access counting, you
must provide some external logic to generate a modified DBGACK that always falls
after three instruction fetches.
When system speed accesses occur, DBGACK remains HIGH throughout. It then falls
after the system speed memory accesses are completed, and finally rises again as the
processor reenters debug state. Therefore, DBGACK masks all system speed memory
accesses.
Internal Cycles
Note
Copyright © 2000 ARM Limited. All rights reserved.
IAb
N
IAb+4
S
IAb+8
S
Figure C-5 Debug exit sequence
ARM DDI 0165B
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