SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 83
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SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 83 of 290
- Download datasheet (5Mb)
4.5
ARM DDI 0165B
Endian effects for instruction fetches
The ARM9E-S performs 32-bit or 16-bit instruction fetches depending on whether the
processor is in ARM or Thumb state. The processor state can be determined externally
by the value of the ITBIT signal. When this signal is LOW, the processor is in ARM
state, and 32-bit instructions are fetched. When ITBIT is HIGH, the processor is in
Thumb state and 16-bit instructions are fetched.
The address produced by the ARM9E-S is always halfword-aligned. However, the
memory system must ignore bit 1of the address, depending on the size of the instruction
request. The significant address bits are listed in Table 4-3.
When a halfword instruction fetch is performed, a 32-bit memory system can return the
complete 32-bit word, and the ARM9E-S extracts the valid halfword field from it. The
field extracted depends on the state of the CFGBIGEND signal, which determines the
endianness of the system (see Memory formats on page 2-4).
The fields extracted by the ARM9E-S are shown in Table 4-4.
When connecting 8-bit or 16-bit memory systems to the ARM9E-S, ensure that the data
is presented to the correct byte lanes on the ARM9E-S as shown in Table 4-5.
ITBIT
0
ITBIT
1
1
Copyright © 2000 ARM Limited. All rights reserved.
IA[1]
X
IA[1]
0
1
Little-endian
CFGBIGEND = 0
INSTR[31:0]
Little-endian
CFGBIGEND = 0
INSTR[15:0]
INSTR[31:16]
ITBIT
1
0
Table 4-4 32-bit instruction fetches
Table 4-3 Significant address bits
Width
Halfword
Word
Table 4-5 Halfword accesses
Big-endian
CFGBIGEND = 1
INSTR[31:0]
Big-endian
CFGBIGEND = 1
INSTR[31:16]
INSTR[15:0]
Significant
address bits
IA[31:1]
IA[31:2]
Memory Interface
4-7
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