SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 86
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
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- Download datasheet (5Mb)
Memory Interface
4.6.2
4-10
Instruction interface, sequential cycles
Sequential instruction fetches are used to perform burst transfers on the bus. This
information can be used to optimize the design of a memory controller interfacing to a
burst memory device, such as a DRAM.
During a sequential cycle, the ARM9E-S requests a memory location that is part of a
sequential burst. If this is the first cycle in the burst, the address might be the same as
the previous internal cycle. Otherwise the address is incremented from the previous
instruction fetch that was performed:
•
•
The types of bursts are shown in Table 4-7.
All accesses in a burst are of the same width, direction, and protection type. For more
details, see Instruction interface addressing signals on page 4-4.
Bursts of byte accesses are not possible with the instruction memory interface.
A burst always starts with an N cycle, or a merged I-S cycle (see Instruction interface,
merged I-S cycles on page 4-11), and continues with S cycles. A burst comprises
transfers of the same type or size. The IA[31:1] signal increments during the burst. The
other address class signals are unaffected by a burst.
An example of a burst access is shown in Figure 4-3 on page 4-11.
Burst type
Word read
Halfword read
for a burst of word accesses, the address is incremented by 4 bytes
for a burst of halfword access, the address is incremented by 2 bytes.
Copyright © 2000 ARM Limited. All rights reserved.
Address
increment
4 bytes
2 bytes
Cause
Thumb code fetches
ARM code fetches
Table 4-7 Burst types
ARM DDI 0165B
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