SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 331

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SAM3SD8B

Manufacturer Part Number
SAM3SD8B
Description
Manufacturer
Atmel Corporation
Datasheets
20.4
20.4.1
20.4.2
20.5
20.5.1
20.5.2
331
331
Product Dependencies
CRCCU Functional Description
SAM3S8/SD8
SAM3S8/SD8
Power Management
Interrupt Source
CRC Calculation Unit description
CRC Calculation Unit Operation
The CRCCU is clocked through the Power Management Controller (PMC), the programmer
must first configure the CRCCU in the PMC to enable the CRCCU clock.
The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU
interrupt requires programming the Interrupt Controller before configuring the CRCCU.
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured
and activated, this CRC engine performs a checksum computation on a Memory Area. CRC
computation is performed from the LSB to MSB bit. Three different polynomials are available
CCITT802.3, CASTAGNOLI and CCITT16, see the bitfield description,
nomial” on page
The CRCCU has a DMA controller that supports programmable CRC memory checks. When
enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped
in the internal SRAM. The addresses of these two registers are pointed at by the
CRCCU_DSCR register.
Table 20-1.
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the
transfer-completed interrupt enable.
To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode
Register (CRCCU_MR), then configure it and finally set the DMA enable bit (DMAEN) in the
CRCCU DMA Enable Register (CRCCU_DMA_EN).
CRCCU_DSCR+0x0
CRCCU_DSCR+0x4
CRCCU_DSCR+0x8
CRCCU_DSCR+0xC
CRCCU_DSCR+0x20
CRCCU Descriptor Memory Mapping
347, for details.
---->
---->
---->
---->
---->
TR_ADDR
TR_CTRL
Reserved
Reserved
TR_CRC
Memory
SRAM
“PTYPE: Primitive Poly-
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12

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