SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 896

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

Figure 35-15. Comparison Waveform
896
896
Comparison Update
Comparison Match
SAM3S8/SD8
SAM3S8/SD8
CVMVUPD
CUPRUPD
CUPRCNT
CPRUPD
CTRUPD
CPRCNT
CVUPD
CCNT0
CMPM
CMPU
CUPR
CVM
CPR
CTR
CV
0x6
0x1
0x1
0x3
0x6
0x1
0x1
0x3
0x0
0x0
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the field CUPR in the PWM_CMPMx.
The comparison unit has an update period counter independent from the period counter to trig-
ger this update. When the value of the comparison update period counter CUPRCNT (in
PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x
update period CUPR itself can be updated while the channel 0 is enabled by using the
PWM_CMPMUPDx register.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be fol-
lowed by a write of the register PWM_CMPMUPDx.
The comparison match and the comparison update can be source of an interrupt, but only if it is
enabled and not masked. These interrupts can be enabled by the
ter 2”
and the comparison update interrupt are reset by reading the
.
and disabled by the
0x1
0x1
0x2
0x2
0x0
0x2
0x3
0x2
0x3
0x1
“PWM Interrupt Disable Register 2”
0x2
0x2
0x2
0x0
0x0
0x3
0x1
0x1
0x2
0x2
0x0
0x3
0x6
0x1
0x0
“PWM Interrupt Status Register 2”
. The comparison match interrupt
0x2
0x1
“PWM Interrupt Enable Regis-
0x6
0x0
0x2
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
0x1
0x3