SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1125

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

39.6.2.5
Name:
Address:
Access:
• DMA_x: DMA Channel x Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when DMA_x bit in UOTGHS_DEVIER is written to one.
This bit is cleared when DMA_x bit in UOTGHS_DEVIDR is written to one.
• PEP_x: Endpoint x Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when PEP_x bit in UOTGHS_DEVIER is written to one.
This bit is cleared when PEP_x bit in UOTGHS_DEVIDR is written to one.
• UPRSME: Upstream Resume Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when UPRSMES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when UPRSMEC bit in UOTGHS_DEVIDR is written to one.
• EORSME: End of Resume Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when EORSMES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when EORSMEC bit in UOTGHS_DEVIDR is written to one.
• WAKEUPE: Wake-Up Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when WAKEUPES bit in UOTGHS_DEVIER is written to one.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
PEP_3
31
23
15
–
–
7
–
Device Global Interrupt Mask Register
UOTGHS_DEVIMR
0x400AC010
Read-only
UPRSME
DMA_6
PEP_2
30
22
14
–
6
EORSME
DMA_5
PEP_9
PEP_1
29
21
13
5
WAKEUPE
DMA_4
PEP_8
PEP_0
28
20
12
4
EORSTE
DMA_3
PEP_7
27
19
11
–
3
DMA_2
PEP_6
SOFE
26
18
10
–
2
MSOFE
DMA_1
PEP_5
25
17
9
–
1
SAM3X/A
SAM3X/A
SUSPE
PEP_4
24
16
–
8
–
0
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