SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1131

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

39.6.2.8
Name:
Address:
Access:
• EPRSTx: Endpoint x Reset
Writing a one to this bit will reset the endpoint x FIFO prior to any other operation, upon hardware reset or when a USB bus
reset has been received. This resets the endpoint x registers (UOTGHS_DEVEPTCFGx, UOTGHS_DEVEPTISRx,
U O T G H S _ D E V E P T I M R x ) b u t n o t t h e e n d p o i n t c o n f i g u r a t i o n ( U O T G H S _ D E V E P T C F G x . A L L O C ,
U O T G H S _ D E V E P T C F G x . E P B K , U O T G H S _ D E V E P T C F G x . E P S I Z E , U O T G H S _ D E V E P T C F G x . E P D I R ,
UOTGHS_DEVEPTCFGx.EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence
field (UOTGHS_DEVEPTISRx.DTSEQ) which can be cleared by setting the UOTGHS_DEVEPTIMRx.RSTDT bit (by writ-
ing a one to the UOTGHS_DEVEPTIERx.RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
• EPENx: Endpoint x Enable
0: The endpoint x is disabled, what forces the endpoint x state to inactive (no answer to USB requests) and resets the end-
point x registers (UOTGHS_DEVEPTCFGx, UOTGHS_DEVEPTISRx, UOTGHS_DEVEPTIMRx) but not the endpoint
configuration (UOTGHS_DEVEPTCFGx.ALLOC, UOTGHS_DEVEPTCFGx.EPBK, UOTGHS_DEVEPTCFGx.EPSIZE,
UOTGHS_DEVEPTCFGx.EPDIR, UOTGHS_DEVEPTCFGx.EPTYPE).
1: The endpoint x is enabled.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
EPRST7
EPEN7
31
23
15
–
–
7
Device Endpoint Register
UOTGHS_DEVEPT
0x400AC01C
Read-write
EPRST6
EPEN6
30
22
14
–
–
6
EPRST5
EPEN5
29
21
13
–
–
5
EPRST4
EPEN4
28
20
12
–
–
4
EPRST3
EPEN3
27
19
11
–
–
3
EPRST2
EPEN2
26
18
10
–
–
2
EPRST1
EPEN1
25
17
–
9
–
1
SAM3X/A
SAM3X/A
EPRST8
EPRST0
EPEN8
EPEN0
24
16
8
0
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