SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 62

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

see
11.4.3.8
• ICI
Interruptible-continuable instruction bits, see
• IT
Indicates the execution state bits of the
• T
Always set to 1.
11.4.3.9
11.4.3.10
11.4.3.11
62
62
“Exception types” on page 76
SAM3X/A
SAM3X/A
Execution Program Status Register
Interruptible-continuable instructions
If-Then block
Exception mask registers
The EPSR contains the Thumb state bit, and the execution state bits for either the:
See the register summary in
ments are:
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the opera-
tion that is at fault. See
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
After servicing the interrupt, the processor:
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruc-
tion in the block is conditional. The conditions for the instructions are either all the same, or
some can be the inverse of others. See
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruc-
tion to change the value of PRIMASK or FAULTMASK. See
148, and
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
multiple instruction.
for more information.
“CPS” on page 144
IT
instruction, see
“Interruptible-continuable instructions” on page
“Exception entry and return” on page 80
for more information.
Table 11-2 on page 58
“IT” on page
“IT” on page 138
138.
for the EPSR attributes. The bit assign-
for more information.
“MRS” on page
62.
147,
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
“MSR” on page