AD6672 Analog Devices, AD6672 Datasheet
AD6672
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... REQUANTIZER AD6672 REFERENCE 1-TO-8 CLOCK DIVIDER SERIAL PORT SCLK SDIO CSB CLK+ Figure 1. AD6672 supports enhanced SNR performance within a AD6672 ©2011 Analog Devices, Inc. All rights reserved. AD6672 DCO± 0/D0± D9±/D10± OR± CLK– can achieve AD6672 www.analog.com ...
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... AD6672 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ............................................................... 5 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 15 Theory of Operation ...
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... MHz at 250 MSPS. 5. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. Rev Page AD6672 ...
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... AD6672 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error ...
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... Full 25°C −88 25°C 88 25°C 88 25°C 89 25°C 87 Full 80 25°C 88 Rev Page AD6672 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS ...
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... AD6672 1 Parameter WORST OTHER (HARMONIC OR SPUR MHz MHz 140 MHz 185 MHz 220 MHz IN TWO-TONE SFDR f = 184.12 MHz, 187.12 MHz (−7 dBFS FULL POWER BANDWIDTH 3 NOISE BANDWIDTH 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. ...
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... Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Rev Page AD6672 Min Typ Max Unit CMOS/LVDS/LVPECL 0.9 V 0.3 3.6 V p-p AGND AVDD V 0.9 1 +22 μA −22 −10 μA 4 ...
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... AD6672 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 Mode Aperture Delay ( Aperture Uncertainty (Jitter, t ...
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... Time required for the SDIO pin to switch from an input to an output EN_SDIO relative to the SCLK falling edge (not shown in Figure 42) t Time required for the SDIO pin to switch from an output to an input DIS_SDIO relative to the SCLK rising edge (not shown in Figure 42) Rev Page AD6672 Min Typ Max Unit ...
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... AD6672 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND 0/D0−, 0/D0 + Through D9−/D10−, D9+/D10+ to AGND OR+/OR− to AGND DCO+, DCO− to AGND Environmental ...
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... DDR LVDS Output Data 9/10—True. Output DDR LVDS Output Data 9/10—Complement. Output LVDS Data Clock Output—True. Output LVDS Data Clock Output—Complement. Input SPI Serial Clock. Input/output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Rev Page AD6672 ...
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... AD6672 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, T unless otherwise noted. 0 250MSPS 30.1MHz @ –1.0dBFS SNR = 65.6dB (66.6dBFS) –20 SFDR = 88dBc –40 –60 SECOND HARMONIC –80 –100 –120 –140 0 10 ...
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... FREQUENCY (Hz) = 89.12 MHz, f IN1 IN2 0 250MSPS 184.12MHz @ –7.0dBFS 187.12MHz @ –7.0dBFS SFDR = 86dBc (93dBFS 100 FREQUENCY (Hz) = 184.12 MHz, f IN1 IN2 AD6672 –21.0 –9 110 120 = 92.12 MHz 110 120 = 187.12 MHz ...
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... AD6672 100 SFDR (dBc SNR (dBFS 100 120 140 160 SAMPLE RATE (MSPS) Figure 16. Single-Tone SNR/SFDR vs. Sample Rate (f 180 200 220 240 ) with MHz S IN Rev Page 1000 0.65LSB RMS 16384 TOTAL HITS 9000 ...
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... Figure 20. Equivalent LVDS Output Circuit AVDD CLK– Rev Page DRVDD 350Ω SDIO 26kΩ Figure 21. Equivalent SDIO Circuit 350Ω SCLK 26kΩ Figure 22. Equivalent SCLK Input Circuit AVDD 26kΩ 350Ω CSB Figure 23. Equivalent CSB Input Circuit AD6672 ...
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... During power-down, the output buffers go into a high impedance state. The AD6672 features a noise shaping requantizer (NSR) to allow higher than 11-bit SNR to be maintained in a subset of the Nyquist band. ...
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... P A the true SNR performance of the AD6672. For applications where SNR is a key parameter, differential double balun coupling is AD6672 the recommended input configuration (see Figure 28). In this configuration, the input is ac-coupled and the VCM voltage is provided to the input through a 33 Ω ...
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... AD6672 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6672. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT CONSIDERATIONS For optimum performance, the AD6672 CLK+ and CLK− ...
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... Figure 34. SNR vs. Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD6672, treat the clock input as an analog signal. In addition, use separate power supplies for the clock drivers and the ADC output driver to avoid modulating the clock signal with digital noise ...
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... Minimize the length of the output data lines as well as the loads placed on these lines to reduce transients within the AD6672. Note, Interfacing to High These transients may degrade converter dynamic performance. The lowest typical conversion rate of the clock rates below 40 MSPS, dynamic performance may degrade ...
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... Figure 37. 22% Bandwidth Mode, Tuning Word = 28 0 250MSPS 180.1MHz @ –1.6BFS –20 SNR = 73.3dB (74.9dBFS) SFDR = 92dBc (IN BAND) –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 38. 22% Bandwidth Mode, Tuning Word = 41 AD6672 with the 33% bandwidth NSR mode AD6672 100 125 100 125 ...
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... AD6672 0 250MSPS 180.1MHz @ –1.6BFS –20 SNR = 71.1dB (72.7dBFS) SFDR = 92dBc (IN BAND) –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 39. 33% Bandwidth Mode, Tuning Word = 5 0 250MSPS 180.1MHz @ –1.6BFS –20 SNR = 71.2dB (72.8dBFS) SFDR = 92dBc (IN BAND) –40 – ...
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... The pins described in Table 11 comprise the physical interface between the user programming device and the serial port of the AD6672. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6672 part-specific features are described in the Memory Map Register Description section. Table 12. Features Accessible Using the SPI Feature Name Mode ...
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... Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Rev Page AD6672 ...
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... BIST enable Open Open Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD6672 = 0xA4) (default) Speed grade ID Open Open 00 = 250 MSPS Open Open Open Open Open Open Open Open Open Open Open Open ...
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... Open Open NSR mode 000 = 22% bandwidth mode 001 = 33% bandwidth mode NSR tuning word (see the Noise Shaping Requantizer section; equations for the tuning word are dependent on the NSR mode) Rev Page AD6672 Default Default Bit 0 Value Notes/ Bit 1 (Hex) Comments ...
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... AD6672 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application to High Speed ADCs via SPI. NSR Control (Register 0x3C) Bits[7:4]—Reserved Bits[3:1]—NSR Mode Bits[3:1] determine the bandwidth mode of the NSR. When Bits[3:1] are set to 000, the NSR is configured for 22% bandwidth mode, which provides enhanced SNR performance over 22% of the sample rate ...
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... Power and Ground Recommendations When connecting power to the AD6672 recommended that two separate 1.8 V supplies be used: use one supply for analog (AVDD) and a separate supply for the digital outputs (DRVDD). ...
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... Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ × Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board with AD6672 and Software Rev Page 3.75 EXPOSED PAD 3 ...
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... NOTES Rev Page AD6672 ...
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... AD6672 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09997-0-7/11(0) Rev Page ...