AD6672 Analog Devices, AD6672 Datasheet - Page 8

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6672
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
1
Timing Diagram
Conversion rate is the clock rate after the divider.
Data Propagation Delay (t
DCO Propagation Delay (t
DCO-to-Data Skew (t
Out-of-Range Recovery Time
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Pipeline Delay (Latency)—NSR Disabled
Pipeline Delay (Latency)—NSR Enabled
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
ODD/EVEN
D9±/D10±
(MSB)
DCO–
DCO+
0/D0±
(LSB)
CLK+
CLK–
1
A
VIN
)
SKEW
CH
)
)
DCO
PD
)
)
N – 1
J
)
CLK
t
CH
)
t
A
t
t
N
PD
DCO
N – 10
N – 10
t
CLK
D9
Figure 2. LVDS Data Output Timing
0
t
SKEW
N – 10
N – 10
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N + 1
D10
D0
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
N – 9
N – 9
D9
0
N – 9
N – 9
N + 2
D10
D0
Min
40
4
1.8
1.9
0.8
4.1
4.7
0.3
N – 8
N – 8
D9
0
N – 8
N – 8
N + 3
D10
D0
Typ
2.0
2.0
1.0
0.1
4.7
5.3
0.5
10
13
10
100
3
N – 7
N – 7
D9
0
N – 7
N – 7
N + 4
D10
D0
Max
625
250
2.2
2.1
5.2
5.8
0.7
N – 6
N – 6
D9
0
N + 5
Unit
MSPS
ns
ns
ns
ns
ps rms
ns
ns
ns
Cycles
Cycles
μs
μs
Cycles
MHz
ns