AD7607 Analog Devices, AD7607 Datasheet - Page 25

• Manufacturer Part Number: AD7607
• Description: 8-Channel DAS with 14-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7607

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

Data Sheet
Figure 42 shows a read of eight simultaneous conversion results
using two D
transfer is used to access data from the AD7607, and CS is held
low to frame the entire 56 SCLK cycles. Data can also be clocked
out using just one D
that D
channel data is output in ascending order. For the AD7607 to
access all eight conversion results on one D
112 SCLK cycles are required. These 112 SCLK cycles can be
framed by one CS signal, or each group of 14 SCLK cycles can be
individually framed by the CS signal. The disadvantage of using
just one D
if reading occurs after conversion. The unused D
be left unconnected in serial mode. If D
single D
order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the
FRSTDATA indicator returns low after V5 is read on D
Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the AD7607 in serial mode.
The SCLK input signal provides the clock source for the serial
read operation. The CS goes low to access the data from the
AD7607. The falling edge of CS takes the bus out of three-state
and clocks out the MSB of the 14-bit conversion result. This
MSB is valid on the first falling edge of the SCLK after the CS
falling edge.
OUT
OUT
A be used to access all conversion data because the
OUT
line, the channel results are output in the following
OUT
line is that the throughput rate is reduced
lines on the AD7607. In this case, a 56 SCLK
OUT
line; in which case, it is recommended
D
D
SCLK
OUT
OUT
CS
A
B
OUT
OUT
B is to be used as a
line, a total of
OUT
V1
V5
Figure 42. Serial Interface with Two D
line should
OUT
B.
Rev. B | Page 25 of 32
V2
V6
The subsequent 13 data bits are clocked out of the AD7607 on the
SCLK rising edge. Data is valid on the SCLK falling edge. To access
each conversion result, 14 clock cycles must be provided.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of CS
takes FRSTDATA out of three-state and sets the FRSTDATA pin
high, indicating that the result from V1 is available on the D
output data line. The FRSTDATA output returns to a logic low
following the 14
D
on this serial data output pin. It goes high only when V1 is available
on D
READING DURING CONVERSION
Data can be read from the AD7607 while BUSY is high and the
conversions are in progress. This has little effect the performance
of the converter, and it allows a faster throughput rate to be
achieved. A parallel, parallel byte, or serial read can be performed
during conversions and when oversampling is or is not enabled.
Figure 3 shows the timing diagram for reading while BUSY is
high in parallel or serial mode. Reading during conversions
allows the full throughput rate to be achieved when using the
serial interface with V
Data can be read from the AD7607 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t
outlined in Table 3, should be observed in this condition.
V3
V7
OUT
B, the FRSTDATA output does not go high when V1 is output
OUT
OUT
A (and this is when V5 is available on D
Lines
V4
V8
th
SCLK falling edge. If all channels are read on
56
DRIVE
above 3.3 V.
OUT
B).
AD7607
OUT
6
, as
A