AD6659 Analog Devices, AD6659 Datasheet
AD6659
Specifications of AD6659
Related parts for AD6659
AD6659 Summary of contents
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... CLK+ CLK– SYNC DCS Figure 1. PRODUCT HIGHLIGHTS 1. The AD6659 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. SPI-selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth MHz at 80 MSPS ...
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... AD6659 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 14 Theory of Operation ...
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... The NSR block is programmed to provide a bandwidth of 20% of the sample clock. For example, with a sample clock rate of 80 MSPS, the AD6659 can achieve up to 81.5 dBFS SNR for a 16 MHz bandwidth at 9.7 MHz AIN. With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 12 bits ...
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... AD6659 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error 1 Gain Error 2 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL) MATCHING CHARACTERISTICS Offset Error ...
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... Full 71.5 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C Full 80 25°C 25°C 25°C Full 25°C Full 25°C Rev. | Page AD6659 Typ Max Unit 72.4 dBFS 72.3 dBFS 72.0 dBFS dBFS 81.5 dBFS 81.2 dBFS 80.3 dBFS 72.4 dBFS 72.2 dBFS 71.9 dBFS dBFS 11.7 Bits 11 ...
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... AD6659 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Current ...
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... N – Figure 2. CMOS Output Data Timing Rev. | Page Min Typ Max Unit 480 MHz 3 80 MSPS 12.5 ns 6.25 ns 1.0 ns 0.1 ps rms 0 Cycles 10 Cycles 11 Cycles 350 μs 260 ns 2 Cycles – – – 5 AD6659 ...
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... AD6659 VIN CLK+ CLK– DCOA/DCOB CH A/CH B DATA TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time (see Figure 4) SSYNC t SYNC to rising edge of CLK hold time (see Figure 4) HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK (see Figure 50) ...
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... Rev. | Page specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the Airflow Velocity (m/sec) θ θ 23°C /W 2.0° C/W 1.0 20°C/W 2.5 18°C/W EC 25-5 2S2P test board. oving air). AD6659 1, 4 θ 2°C/W ...
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... SDIO/DCS 45 SCLK/DFS 46 CSB 47 OEB 48 PDWN CLK+ 1 PIN 1 INDICATOR CLK– 2 SYNC AD6659 TOP VIEW D1B 9 (Not to Scale) 10 D2B 11 D3B 12 D4B 13 D5B 14 D6B 15 D7B 16 Figure 5. Pin Configuration Description Exposed paddle is the only ground connection for the chip. It must be connected to the printed circuit board (PCB) AGND ...
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... Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev. | Page AD6659 ...
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... AD6659 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted 80MSPS 9.7MHz @ –1dBFS –20 SNR = 70.2dB (71.2dBFS) SFDR = 93.6dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 6 ...
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... SFDRFS 80 SNRFS 60 SFDR SNR –70 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBc) Figure 15. SNR/SFDR vs. Input Amplitude (AIN) with f 0.4 0.2 0 –0.2 –0.4 0 500 1000 1500 2000 2500 3000 OUTPUT CODE Figure 16. INL Error with f = 9.7 MHz IN AD6659 – 9.7 MHz IN 3500 4000 ...
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... AD6659 EQUIVALENT CIRCUITS AVDD VIN±x Figure 17. Equivalent Analog Input Circuit AVDD 5Ω CLK+ 15kΩ AVDD 15kΩ 5Ω CLK– Figure 18. Equivalent Clock Input Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ Figure 19. Equivalent SDIO/DCS Input Circuit DRVDD Figure 20 ...
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... AVDD 375Ω VREF 7.5kΩ Figure 25. Equivalent VREF Circuit Rev. | Page AD6659 ...
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... During power-down, the output buffers go into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD6659 is a differential switched capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal dependent errors and achieve optimum performance ...
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... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD6659 (see Figure 28), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... AD6659 0.1µF 2V p-p P 0.1µF ANALOG INPUT C D ANALOG INPUT 0.1µF 0.1µF 25Ω 0.1µF 25Ω 0.1µF Figure 31. Differential Double Balun Input Configuration V CC 0Ω 0.1µ 0.1µ 200Ω AD8352 200Ω 0.1µ 0Ω 0.1µF Figure 32 ...
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... SELECT LOGIC SENSE Figure 33. Internal Reference Configuration If the internal reference of the AD6659 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 shows how the internal reference voltage is affected by loading. Table 10. Reference Configuration Summary ...
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... Jitter Considerations section. Figure 37 and Figure 38 show two preferred methods for clocking the AD6659 (at clock rates up to 480 MHz before the internal CLK divider). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun ...
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... Treat the clock input as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD6659. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal controlled oscillators make the best clock sources ...
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... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD6659. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6659 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCOx) The AD6659 provides two data clock output (DCOx) signals intended for capturing the data in an external register ...
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... Offset Binary Output Mode Twos Complement Mode 0000 0000 0000 1000 0000 0000 0000 0000 0000 1000 0000 0000 1000 0000 0000 0000 0000 0000 1111 1111 1111 0111 1111 1111 1111 1111 1111 0111 1111 1111 Rev. | Page AD6659 ...
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... AD6659. BIST The BIST is a thorough test of the digital portion of the selected AD6659 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... CHANNEL/CHIP SYNCHRONIZATION The AD6659 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock ...
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... NSR Mode Bits[2:1] in the 0x11E SPI register. Figure 45 to Figure 47 shows the typical spectrum that can be expected from the AD6659 with the 20% BW NSR mode enabled for the three different filter settings. 0 80MSPS – ...
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... QEC functions (dc, gain, or phase correction) are used. QEC and DC Correction Range Table 13 gives the minimum and maximum correction ranges of the QEC algorithms on the AD6659; if the mismatches are greater than these ranges, an imperfect correction results. Table 13. QEC and DC Correction Range Parameter ...
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... AD6659 0 –15 –30 –45 DC –60 –75 – –105 –120 –135 FREQUENCY (MHz) Figure 48. QEC Mode Off 0 –15 –30 IMAGE –45 –60 –75 – –105 –120 –135 Rev. | Page IMAGE FREQUENCY (MHz) Figure 49. QEC Mode On ...
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... SERIAL PORT INTERFACE (SPI) The AD6659 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from the port ...
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... The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD6659. When using the SPI interface, SCLK and CSB function as inputs. SDIO is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD6659 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). ...
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... Clock (global) Open Open 0x0B Clock divide (global) Bit 5 Bit 4 Bit 3 Soft reset 1 1 8-bit Chip ID Bits[7:0] AD6659 = 0x76 Speed Grade ID[6:4] 80 MSPS = 011 Open Open Open Open Open Open Open Open 0x01 standby (local) Open Open Open Rev. | Page ...
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... Enable data Open Open DCO/Data Delay[2:0] delay Rev. | Page AD6659 Default Bit 0 Value Bit 1 (LSB) (Hex) Comments 0x00 When set, the test data is placed on the output pins in place of normal ...
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... AD6659 Addr Bit 7 (Hex) Register Name (MSB) Bit 6 0x1A USER_PATT1_MSB B15 B14 0x1B USER_PATT2_LSB B7 B6 0x1C USER_PATT2_MSB B15 B14 0x24 BIST signature LSB 0x2A Features Open Open 0x2E Output assign Open Open Digital Feature Control Registers 0x100 Sync control Open Open ...
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... These bits adjust the time constants of the phase control feedback loop for quadrature error correction. QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—Kexp_DC[4:0] These bits adjust the time constants of the dc control feedback loop for quadrature error correction. Rev. | Page AD6659 ...
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... AD6659 QEC Initial Gain 0 and QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain[14:0] When the force gain bit (Register 0x111, Bit 0) is set high, these values are used for gain error correction. QEC Initial Phase 0 and QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]— ...
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... APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD6659 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD6659 strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD) ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD6659BCPZ-80 –40°C to +85°C AD6659BCPZRL7-80 –40°C to +85°C AD6659-80EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only ground connection on the chip and must be connected to the PCB AGND. 9.00 BSC SQ 0.60 MAX ...
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... NOTES Rev. | Page AD6659 ...
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... AD6659 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08701-0- /10(0) Rev. | Page ...