AD9272 Analog Devices, AD9272 Datasheet - Page 39
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AD9272
Manufacturer Part Number
AD9272
Description
Octal LNA/VGA/AAF/ADC and Crosspoint Switch
Manufacturer
Analog Devices
Datasheet
1.AD9272.pdf
(44 pages)
Specifications of AD9272
Resolution (bits)
12bit
# Chan
8
Sample Rate
80MSPS
Interface
LVDS,Ser
Analog Input Type
SE-Uni
Ain Range
367 mV p-p,550 mV p-p,733 mV p-p
Adc Architecture
Pipelined
Pkg Type
QFP
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Table 16. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
SCLK
SDIO
CSB
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
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0
10
NUMBER OF SDIO PINS CONNECTED TOGETHER
t
20
S
Figure 68. SDIO Pin Loading
R/W
Minimum Timing (ns)
5
2
40
5
2
16
16
10
10
30
t
DS
W1
40
50
W0
t
DH
60
A12
70
A11
t
80
HI
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
90
A10
Figure 69. Serial Timing Details
t
100
LO
A9
Rev. C | Page 39 of 44
t
CLK
A8
A7
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
D5
D4
D3
D2
D1
D0
t
H
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AD9272