AD7991 Analog Devices, AD7991 Datasheet - Page 8

• Manufacturer Part Number: AD7991
• Description: 4-Channel, 12-Bit ADC with I2C Compatible Interface in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7991

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 140kSPS
• Interface: I²C/Ser 2-Wire
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

AD7991/AD7995/AD7999
Parameter
LOGIC INPUTS (SDA, SCL)
LOGIC OUTPUTS (OPEN
DRAIN)
THROUGHPUT RATE
POWER REQUIREMENTS
1
2
3
4
5
6
7
8
Functional from V
A Version tested at V
Sample delay and bit trial delay enabled, t
For f
See the Terminology section.
For f
Guaranteed by initial characterization.
See the Reading from the AD7991/AD7995/AD7999 section.
Power Dissipation
Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, I
Input Capacitance, C
Input Hysteresis, V
Output Low Voltage, V
Floating-State Leakage
Floating-State Output
Output Coding
V
I
DD
DD
ADC Operating,
Current
Capacitance
Power-Down,
Power-Down ,
ADC Operating,
Power-Down,
SCL
SCL
Power-Down ,
Interface Active
(Fully Operational)
up to 400 kHz, clock stretching is not implemented. Above f
≤ 1.7 MHz, clock stretching is not implemented; for f
Interface Active
(Fully Operational)
Interface Active
Interface Inactive
Interface Active
Interface Inactive
7
DD
= 2.35 V.
DD
HYST
=3.3 V and f
INL
IN
8
3
8
INH
7
8
8
OL
IN
Min
0.7 (V
0.1 (V
2.7
SCL
Straight (natural) binary
= 3.4 MHz. Functionality tested at f
DD
DD
)
)
A Version
Typ
1
= t
2
= 0.5/f
Max
0.3 (V
±1
10
0.4
0.6
±1
10
18×(1/f
17.5×(1/f
+ 2 μs
5.5
0.25
0.26
1
0.83
0.86
3.3
2
SCL
.
DD
SCL
SCL
)
SCL
)
> 1.7 MHz, clock stretching is implemented.
)
SCL
Min
0.7 (V
0.9 (V
0.1 (V
2.7
Straight (natural) binary
= 400 kHz, clock stretching is implemented.
SCL
Rev. B | Page 8 of 28
DD
DD
DD
= 400 kHz.
)
)
)
Y Version
Typ
Max
0.3 (V
0.1 (V
±1
10
0.4
0.6
±1
10
18×(1/f
17.5×(1/f
+ 2 μs
5.5
0.09/0.25
0.25/0.8
0.07/0.16
0.26/0.85
1/1.6
0.3/1.38
0.83/4.4
0.24/0.88
0.86/4.68
3.3/8.8
DD
DD
SCL
)
)
SCL
)
)
Unit
V
V
V
V
μA
pF
V
V
V
μA
pF
V
mA
mA
mA
mA
μA
mW
mW
mW
mW
μW
Test Conditions/Comments
V
V
V
V
V
I
I
f
f
V
clock stretching is implemented
Digital inputs = 0 V or V
V
V
V
V
V
V
V
V
V
V
SINK
SINK
SCL
SCL
DD
DD
DD
DD
IN
REF
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 0 V or V
≤ 1.7 MHz; see the
> 1.7 MHz; see the
= 2.7 V to 5.5 V
= 2.35 V to 2.7 V
= 2.7 V to 5.5 V
= 2.35 V to 2.7 V
= 3.3 V/5.5 V, 400 kHz f
= 3.3 V/5.5 V, 3.4 MHz f
= 3.3 V/5.5 V, 400 kHz f
= 3.3 V/5.5 V, 3.4 MHz f
= 3.3 V/5.5 V
= 3.3 V/5.5 V, 400 kHz f
= 3.3 V/5.5 V, 3.4 MHz f
= 3.3 V/5.5 V, 400 kHz f
= 3.3 V/5.5 V, 3.4 MHz f
= 3.3 V/5.5 V
= 3 mA
= 6 mA
= V
DD
; for f
DD
SCL
= 3.4 MHz,
Serial Interface
Serial Interface
DD
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
section
section