AD9601 Analog Devices, AD9601 Datasheet - Page 20

• Manufacturer Part Number: AD9601
• Description: 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9601

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,1.25 V p-p,1.5 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9601
LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9601, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V nominal). If only a
single 1.8 V supply is available, it is routed to AVDD first, then
tapped off and isolated with a ferrite bead or filter choke with
decoupling capacitors proceeding connection to DRVDD. The
user can employ several different decoupling capacitors to cover
both high and low frequencies. These should be located close to
the point of entry at the PC board level and close to the parts
with minimal trace length.
A single PC board ground plane is sufficient when using the
AD9601. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9601. An
exposed, continuous copper plane on the PCB should mate to
the AD9601 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie
point between the ADC and PCB. See Figure 43 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 45.
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 43. Typical PCB Layout
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RBIAS
The AD9601 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
AD9601 CONFIGURATION USING THE SPI
The AD9601 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or read back) serially in
one-byte words. Each byte can be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 8).
Table 8. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
RESET
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 44
and Table 10.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.
Function
SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
Master Device Reset. When asserted, device
assumes default settings. Active low.