AD7767 Analog Devices, AD7767 Datasheet
AD7767
Specifications of AD7767
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AD7767 Summary of contents
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... The oversampled architecture also reduces front-end antialias requirements. Other features of the AD7767 include a SYNC / PD (synchronization/power-down) pin, allowing the synchronization of multiple AD7767 devices. The addition of an SDI pin provides the option of daisy chaining multiple AD7767 devices ...
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... Integral Nonlinearity Parameter, Table 2 ................................. 3 Changes to Supply and Reference Voltages Section ................... 16 Changes to Choosing the SCLK Frequency Section .................. 18 Changes to Figure 24 ...................................................................... 12 Changes to Driving the AD7767 Section .................................... 20 Changes to Single-Ended Signal Source Section ........................ 20 Added Figure 41; Renumbered Sequentially .............................. 20 Change to Figure 42 ....................................................................... 21 Added Table 8; Renumbered Sequentially .................................. 20 Replaced V Input Signal Section ...
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... Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) 2 Total Harmonic Distortion (THD) 2 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms AD7767-2 2 Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD Intermodulation Distortion (IMD) Second-Order Terms ...
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... Power-Down Mode Current POWER DISSIPATION AD7767 Operational Power AD7767-1 Operational Power AD7767-2 Operational Power 1 Specifications are for all devices, AD7767, AD7767-1, and AD7767-2. 2 See the Terminology section. Test Conditions/Comments Complete settling Serial 24 bits, twos complement (MSB first +500 μA SINK I = − ...
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... MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum 2 3 MCLK frequency is 1.024 MHz for AD7767 for the AD7767- for the AD7767- common-mode input = V REF , t Unit ...
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... AD7767 TIMING DIAGRAMS 1 MCLK t 1 DRDY Figure 2. DRDY vs. MCLK Timing Diagram for AD7767 (Decimate by 8 for AD7767-1 (Decimate by 16 for AD7767-2 (Decimate by 32) DRDY SCLK t 7 SDO DRDY SCLK DATA SDO MSB INVALID × n ...
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... DRDY (O) VALID DATA DOUT (O) Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section) PART OUT OF POWER-DOWN FILTER RESET BEGINS SAMPLING SETTLING INVALID DATA Rev Page AD7767 t 21 VALID DATA ...
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... AD7767 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter AV to AGND DGND REFGND REF+ REFGND to AGND V to DGND DRIVE AGND IN+ IN– Digital Inputs to DGND Digital Outputs to DGND AGND to DGND Input Current to Any Pin Except ...
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... CS Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on the CS falling edge. The CS input allows multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by supplying it with a logic low CS signal, which enables the SDO pin of the device concerned ...
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... FREQUENCY (Hz) Figure 10. AD7767 FFT, 1 kHz, −6 dB Input Tone 4k 8k 12k 16k 20k 24k 28k FREQUENCY (Hz) Figure 11. AD7767-1 FFT, 1 kHz, −6 dB Input Tone 4k 8k 12k FREQUENCY (Hz) Figure 12. AD7767-2 FFT, 1 kHz, −6 dB Input Tone 64k 32k 1 6k ...
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... FREQUENCY (Hz) Figure 13. AD7767 FFT, 1 kHz, −60 dB Input Tone 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 12k 16k 20k 24k FREQUENCY (Hz) Figure 14. AD7767-1 FFT, 1 kHz, −60 dB Input Tone 0 – ...
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... 140 130 120 110 100 0 10k 20k 30k f (Hz) NOISE Figure 21. AD7767 Power Supply Sensitivity vs. Supply Ripple Frequency (f ) with Decoupling Capacitors NOISE 700k 800k 900k 1 M Figure 22. AD7767 CMRR vs. Common-Mode Ripple Frequency (f 700k 800k 900k 1M V DRIVE 40k ...
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... CODES Figure 26. AD7767/AD7767-1/AD7767-2 24-Bit DNL 3.80 3.04 2.28 1.52 0.76 0 –0.76 –1.52 –2.28 –3.04 –3.80 0 2097152 Figure 27. AD7767/AD7767-1/AD7767-2 24-Bit INL 16777216 14680064 Rev Page AD7767 LOW TEMPERATURE NOMINAL TEMPERATURE HIGH TEMPERATURE 4194304 8388608 12582912 16777216 6291456 10485760 14680064 24-BIT CODES ...
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... The AD7767 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies ...
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... DATA STREAM ( for AD7767 for AD7767- for AD7767-2) Table 6 shows the three available models of the AD7767, listing the change in output data rate relative to the order of decimation rate implemented. This brings into focus the trade-off that exists ...
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... AD7767/AD7767-1/AD7767-2 device. Therefore, when using reference input, the full-scale differential input range of the AD7767/AD7767-1/AD7767 See the Driving the AD7767 section for details on the maximum input voltage. Rev Page and V , Pin 4 and Pin 5, respectively. Using IN+ IN− ...
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... The status of the SYNC / PD pin is checked on each subsequent rising edge of MCLK. On the first rising edge of MCLK after the SYNC / PD pin is taken high, the AD7767 is taken out of power-down. On the next rising edge, the filter of the AD7767 is reset. On the following rising edge, the first new sample is taken ...
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... An example of a daisy chain of four AD7767 devices is shown in Figure 36 and Figure 37. In the case illustrated in Figure 36, the output of the AD7767 labeled A is the output of the full daisy chain. The last device in the chain (the AD7767 labeled D) has its serial data input (SDI) pin connected to ground. All the devices in the chain must use common MCLK, SCLK and SYNC / PD signals ...
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... SCLK SCLK AD7767 (A) SDO (A) SDI (A) = SDO (B) AD7767 (B) AD7767 (C) SDI (B) = SDO (C) SDI (C) = SDO (D) AD7767 (D) Figure 37. Daisy-Chain Timing Diagram ( for AD7767 for AD7767- for AD7767-2) When Driving the AD7767 MCLK DRDY (A) CS SDO (A) MSB (A) SCLK t 16 MSB (B) SDI (A) = SDO (B) ...
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... The common- REF mode voltage of the AD7767 is V /2. When the AD7767 V REF has supply (using ADR445, ADR435, or ADR425), the common mode is at 2.5 V, meaning that the maximum inputs that can be applied on the AD7767 differential inputs are p-p input around 2 REF V REF 2 ...
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... Both the digital and analog currents scale as the MCLK frequency is reduced. The actual throughput equals the MCLK frequency applied divided by the decimation rate employed by the device in use. For instance, operating the AD7767 device with an MCLK of 800 kHz results in an output data rate of 100 kHz due to the decimate-by-8 filtering. ...
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... MCLK frequency and the decimation rate employed by the device in question. For example, applying a 1.024 MHz MCLK frequency to the AD7767 results in a maximum output data rate of 128 kHz, which in turn allows a 1.729 kHz multiplexer switching rate. pin ...
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... Temperature Range AD7767BRUZ −40°C to +105°C AD7767BRUZ-RL7 −40°C to +105°C AD7767BRUZ-1 −40°C to +105°C AD7767BRUZ-1-RL7 −40°C to +105°C AD7767BRUZ-2 −40°C to +105°C AD7767BRUZ-2-RL7 −40°C to +105°C EVAL-AD7767EDZ EVAL-AD7767-1EDZ EVAL-AD7767-2EDZ EVAL-CED1Z RoHS Compliant Part. 5.10 5.00 4. 4.50 6.40 4 ...
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... AD7767 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06859-0-5/10(C) Rev Page ...