AD9271 Analog Devices, AD9271 Datasheet - Page 8

• Manufacturer Part Number: AD9271
• Description: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
• Manufacturer: Analog Devices

Specifications of AD9271

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 50MSPS
• Interface: LVDS,Ser
• Analog Input Type: SE-Uni
• Ain Range: 0.25 V p-p,0.32 V p-p,0.4 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9271
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Can be adjusted via the SPI interface.
Measurements were made using a part soldered to FR-4 material.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data-to-Data Skew (t
Wake-Up Time (Standby), V
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Uncertainty (Jitter)
/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
2
1
F
R
) (20% to 80%)
) (20% to 80%)
2, 3
FRAME
PD
DATA
DATA-MAX
)
)
)
EL
4
4
EH
FCO
CPD
)
)
GAIN
)
− t
)
4
DATA-MIN
= 0.5 V
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Min
50
1.5
1.5
(t
(t
SAMPLE
SAMPLE
Rev. B | Page 8 of 60
/24) − 300
/24) − 300
Typ
10.0
10.0
2.3
300
300
2.3
t
(t
(t
(t
±50
1
1
8
<1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
Max
(t
(t
10
3.1
3.1
±200
SAMPLE
SAMPLE
/24) + 300
/24) + 300
Unit
μs
ms
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
Clock
cycles
ps rms