AD7982 Analog Devices, AD7982 Datasheet - Page 21

• Manufacturer Part Number: AD7982
• Manufacturer: Analog Devices

Specifications of AD7982

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP

CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7982s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7982s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
SDO
ACQUISITION
SDI
A
t
HSCKCNV
= SDI
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing
AD7982
Figure 37. Chain Mode Without Busy Indicator Connection Diagram
D
D
CNV
SCK
1
A
B
A
17
17
t
SSDISCK
D
D
2
A
B
SDO
16
16
D
D
3
A
B
15
15
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t
SCKL
SDI
t
HSDISCK
16
AD7982
CNV
SCK
B
t
D
D
17
CYC
A
B
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7982 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7982s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.
1
1
ACQUISITION
t
SCK
t
SCKH
t
SDO
D
D
18
ACQ
A
B
0
0
D
19
A
17
CONVERT
DATA IN
CLK
DIGITAL HOST
D
20
A
16
34
D
35
A
1
D
36
A
0
AD7982