AD7610 Analog Devices, AD7610 Datasheet - Page 8

• Manufacturer Part Number: AD7610
• Manufacturer: Analog Devices

Specifications of AD7610

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7610
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 3, 42
2, 44
4
5
6, 7, 17
8
9, 10
11, 12
13
Mnemonic
AGND
AVDD
BYTESWAP
OB/2C
OGND
SER/PAR
D[0:1]
D[2:3] or
DIVSCLK[0:1]
D4 or
EXT/INT
Type
P
P
DI
DI
P
DI
DO
DI/O
DI/O
2
1
Description
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to
AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and
OGND voltages should be at the same potential.
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on
D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and
the remaining data bits are high impedance outputs.
Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of
SER/PAR.
In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data
clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or
external (slave) serial data clock for the AD7610 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
D2/DIVSCLK[0]
D3/DIVSCLK[1]
BYTESWAP
SER/PAR
AGND
OB/2C
OGND
OGND
AGND
AVDD
D0
D1
10
11
12
1
2
3
4
5
6
7
8
9
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
Figure 4. Pin Configuration
Rev. 0 | Page 8 of 32
(Not to Scale)
AD7610
TOP VIEW
36
34
28
35
33
32
31
30
29
27
26
25
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D15/SCCS
D14/SCCLK
D13/SCIN
D12/HW/SW