AD9252 Analog Devices, AD9252 Datasheet - Page 18

• Manufacturer Part Number: AD9252
• Description: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9252

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 50MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9252
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference buffer
creates the positive and negative reference voltages, REFT and
REFB, respectively, that define the span of the ADC core. The
output common mode of the reference buffer is set to midsupply,
and the REFT and REFB voltages and span are defined as
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9252, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9252 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the
differential driver to drive the AD9252 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 39) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 36 and Figure 37), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9252.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
1V p-p
0.1μF
120nH
0.1μF
22pF
18nF
Figure 39. Differential Input Configuration Using the
INH
LMD
274Ω
LNA
LON
LOP
AD8334
AD8334
0.1μF
0.1μF
Rev. E | Page 18 of 52
VIP
VIN
VGA
2V p-p
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale input
of 2 V p-p can still be applied to the ADC’s VIN + x pin while the
VIN − x pin is terminated. Figure 38 details a typical single-
ended input configuration.
VOH
VOL
1
2V p-p
1
Figure 37. Differential Transformer-Coupled Configuration for IF Applications
2V p-p
C
C
DIFF
DIFF
65Ω
IS OPTIONAL.
IS OPTIONAL.
16nH
Figure 36. Differential Transformer-Coupled Configuration
187Ω
1kΩ
1kΩ
187Ω
374Ω
AVDD
49.9Ω
49.9Ω
0.1μF
1kΩ
1kΩ
Figure 38. Single-Ended Input Configuration
AD8334
0.1μF
0.1μF
0.1µF
AVDD
1.0kΩ
1.0kΩ
0.1μF
ADT1-1WT
1:1 Z RATIO
ADT1-1WT
1:1 Z RATIO
AVDD
0.1µF
for Baseband Applications
0.1μF
1kΩ 25Ω
1kΩ
1kΩ
1kΩ
0.1μF
R
R
499Ω
AVDD
C
16nH
16nH
10μF
C
C
R
R
DIFF
DIFF
R
2.2pF
33Ω
33Ω
R
C
C
AVDD
1
C
C
1
1kΩ
1kΩ
VIN + x
VIN – x
AD9252
ADC
1kΩ
VIN + x
VIN – x
VIN – x
VIN + x
Data Sheet
AD9252
AD9252
ADC
ADC
VIN+ x
VIN– x
AD9252
AGND
ADC