AD7622 Analog Devices, AD7622 Datasheet - Page 6

• Manufacturer Part Number: AD7622
• Manufacturer: Analog Devices

Specifications of AD7622

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7622
1
2
3
4
5
6
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
See the Conversion Control section.
All timings for wideband warp mode are the same as warp mode.
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
See the Digital Interface section and the RESET section.
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Warp Mode
Normal Mode
TO OUTPUT
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 3. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
SDOUT, SYNC, and SCLK Outputs, C
PIN
50pF
C
L
500µA
500µA
I
I
OL
OH
1.4V
L
= 10 pF
Rev. 0 | Page 6 of 28
Symbol
t
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
28
L
of 10 pF; otherwise, the load is 60 pF maximum.
t
DELAY
0.8V
0
0
3
8
20
2
2
1
0
0
0.64
0.76
Figure 4. Voltage Reference Levels for Timing
0
1
3
16
40
8
8
5
0.5
0.5
0.92
1.04
2V
0.8V
1
0
3
32
60
16
16
15
10
9
1.47
1.59
2V
1
1
3
64
140
32
32
5
28
26
2.57
2.69
t
DELAY
2V
0.8V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs