AD7691 Analog Devices, AD7691 Datasheet - Page 19

• Manufacturer Part Number: AD7691
• Manufacturer: Analog Devices

Specifications of AD7691

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7691 then
enters the acquisition phase and powers down. The data bits
are clocked out, MSB first, by subsequent SCK falling edges.
SDI = 1
ACQUISITION
SDO
CNV
SCK
t
CNVH
CONVERSION
Figure 38. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
t
CONV
1
Rev. B | Page 19 of 28
t
HSDO
D17
2
t
CYC
ACQUISITION
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19
or when CNV goes high, whichever occurs first, SDO returns to
high impedance.
If multiple AD7691s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
D16
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
17
SDI
Figure 37. 3-Wire CS Mode with Busy Indicator
AD7691
t
SCK
CNV
SCK
Connection Diagram (SDI High)
18
D1
SDO
19
D0
VIO
47kΩ
t
DIS
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
th
SCK falling edge,
AD7691