AD9287 Analog Devices, AD9287 Datasheet - Page 21

• Manufacturer Part Number: AD9287
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9287

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 100MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9287 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 42 shows a preferred method for clocking the AD9287. The
low jitter clock source is converted from a single-ended signal to a
differential signal using an RF transformer. The back-to-back
Schottky diodes across the secondary transformer limit clock
excursions into the AD9287 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9287, and it preserves
the fast rise and fall times of the signal, which are critical to low
jitter performance.
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 43. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515
drivers offers excellent jitter performance.
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 45). Although the
CLK+
CLK–
CLK+
CLK–
CLK+
50Ω
50Ω
1
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
1
1
50Ω
Figure 42. Transformer-Coupled Differential Clock
0.1µF
0.1µF
0.1µF
50Ω
0.1µF
0.1µF
50Ω
Figure 44. Differential LVDS Sample Clock
Figure 43. Differential PECL Sample Clock
100Ω
1
1
CLK
CLK
CLK
CLK
ADT1-1WT, 1:1Z
LVDS DRIVER
PECL DRIVER
Mini-Circuits
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
XFMR
0.1µF
240Ω
®
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
family of clock
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD9287
AD9287
AD9287
ADC
ADC
ADC
Rev. E | Page 21 of 52
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals. As a result, these ADCs may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9287 contains a duty cycle stabilizer (DCS) that
retimes the nonsampling edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows a wide range of clock
input duty cycles without affecting the performance of the AD9287.
When the DCS is on, noise and distortion performance are nearly
flat for a wide range of duty cycles. However, some applications
may require the DCS function to be off. If so, keep in mind that
the dynamic range performance can be affected when operated
in this mode. See the Memory Map section for more details on
using this feature.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 20 MHz
nominal. The loop has a time constant associated with it that
must be considered in applications where the clock rate can
change dynamically. This requires a wait time of 1.5 µs to 5 µs
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the period
that the loop is not locked, the DCS loop is bypassed and the
internal device timing is dependent on the duty cycle of the input
clock signal. In such applications, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.
CLK+
CLK+
1
50Ω RESISTORS ARE OPTIONAL.
1
50Ω RESISTORS ARE OPTIONAL.
50Ω
50Ω
0.1µF
0.1µF
Figure 45. Single-Ended 1.8 V CMOS Sample Clock
Figure 46. Single-Ended 3.3 V CMOS Sample Clock
1
1
0.1µF
0.1µF
CLK
CMOS DRIVER
CLK
CLK
CLK
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9287
AD9287
AD9287
ADC
ADC