AD7641 Analog Devices, AD7641 Datasheet - Page 10

• Manufacturer Part Number: AD7641
• Description: 18-Bit, 2 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7641

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 2MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7641
Pin
No.
25 to
28
29
30
31
32
33
34
35
37
38
39
40
43
45
46
47
48
1
Table 7. Data Bus Interface Definition
MODE
0
1
1
2
2
2
2
3
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Mnemonic
D[14:17]
BUSY
DGND
RD
CS
RESET
PD
CNVST
REF
REFGND
IN−
NC
IN+
TEMP
REFBUFIN
PDREF
PDBUF
MODE1
0
0
0
1
1
1
1
1
MODE0
0
1
1
0
0
0
0
1
Type
DO
DO
P
DI
DI
DI
DI
DI
AI/O
AI
AI
AI
AO
AI/O
DI
DI
D0/OB/ 2C
R[0]
OB/ 2C
OB/ 2C
OB/ 2C
OB/ 2C
OB/ 2C
OB/ 2C
OB/ 2C
1
Description
Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
Digital Power Ground.
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
Reset Input. When high, resets the AD7641. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface
section. If not used, this pin can be tied to DGND.
Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
Reference Input Analog Ground.
Differential Negative Analog Input.
No Connect.
Differential Positive Analog Input.
Temperature Sensor Analog Output.
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
D1/A0
R[1]
A0 = 0
A0 = 1
A0 = 0
A0 = 0
A0 = 1
A0 = 1
All Hi-Z
D2/A1
R[2]
R[2]
R[0]
A1 = 0
A1 = 1
A1 = 0
A1 = 1
Rev. 0 | Page 10 of 28
D[3]
R[3]
R[3]
R[1]
All Hi-Z
All Hi-Z
All Hi-Z
All Hi-Z
D[4:9]
R[4:9]
R[4:9]
R[10:11]
R[0:1]
D[10:11]
R[10:11]
R[10:11]
R[2:3]
Serial Interface
All Zeros
All Zeros
R[12:15]
R[12:15]
D[12:15]
R[12:15]
R[4:7]
All Zeros
R[16:17]
D[16:17]
R[16:17]
R[16:17]
R[8:9]
R[0:1]
18-Bit Parallel
16-Bit High Word
16-Bit Low Word
8-Bit High Byte
8-Bit Mid Byte
Description
8-Bit Low Byte
8-Bit Low Byte
Serial Interface