AD7763 Analog Devices, AD7763 Datasheet
AD7763
Specifications of AD7763
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AD7763 Summary of contents
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... V differential-biased around a common mode This common-mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. The AD7763 is available in an exposed paddle, 64-lead TQFP_EP and is specified over the industrial temperature range from −40°C to +85°C. Table 1. Related Devices Part No ...
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... Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 14 AD7763 Interface ............................................................................ 15 Reading Data Using the SPI Interface ..................................... 15 Synchronization .......................................................................... 15 Sharing the Serial Bus ................................................................ 15 Writing to the AD7763 .............................................................. 16 Reading Status and Other Registers ......................................... 17 2 Reading Data Using the I S Interface ....................................... 18 Clocking the AD7763 ..................................................................... 19 Example 1 .................................................................................... 19 REVISION HISTORY 11/09— ...
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... AD7763 Unit dB min dB typ dB typ dBc typ dBc typ dBc typ dB typ dBc typ dBc typ dB min dB typ dB typ dBc typ dB min dB typ dB typ dBc typ dB typ ...
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... SNR specifications in dB are referred to a full-scale input, FS, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 While the AD7763 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 4 Tested with a 400 μA load current. ...
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... DRDY rising edge to SDL falling edge typ SDL pulse width ns max SDO three-state to SCO rising edge min FSI low period ns min SDI setup time ns min SDI hold time ns min FSI setup time typ SDL falling edge to SDL falling edge Rev Page AD7763 ...
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... SDI (I) ALL ADR2 ADR1 t 32 × SCO SCO (O) DRDY A (O) SDO (O) SERIAL DATA FROM ADC A FSO A FSO B FSO C FSO D Figure 4. SPI Interface Serial Read Timing with Multiple AD7763 Devices Sharing the Serial Bus Figure 2. SPI® Interface Serial Read Timing Diagram t 32 × ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 0.3 V DD4 + 0 0.3 V, DD4 Rev Page AD7763 ...
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... − REF DGND 1 PIN 1 2 MCLK DD2 AD7763 DD1 7 TOP VIEW (Not to Scale REF DD4 DD2 AV 15 DD2 THE PCB USING MULTIPLE VIAS ...
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... When the I 2 defined the I S bus specification. See the Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the AD7763 Interface section. Serial Clock Rate. This pin and the CDIV pin program the SCO frequency (see Select ...
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... The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist fre- quency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7763 defined ...
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... FREQUENCY (Hz) 0 –50 –100 –150 –200 –250 0 5000 10000 15000 20000 25000 FREQUENCY (Hz) 0 –50 –100 –150 –200 –250 0 5000 10000 15000 20000 25000 FREQUENCY (Hz) AD7763 30000 35000 30000 35000 30000 35000 ...
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... AD7763 0 –50 –100 –150 –200 –250 0 50000 100000 150000 200000 FREQUENCY (Hz) Figure 12. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation 0 –50 –100 –150 –200 –250 0 50000 100000 150000 200000 FREQUENCY (Hz) Figure 13. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation ...
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... Rev Page 8383091 8383111 8383131 8383151 8383171 24-BIT CODE Figure 21. Low Power 24-Bit Histogram, 256× Decimation +85 ° C +25 ° –40 ° 4194304 8388608 12582912 24-BIT CODE Figure 22. 24-Bit INL, Low Power Mode AD7763 8383191 16777216 ...
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... The AD7763 employs three finite impulse response (FIR) filters in series. By using different combinations of decimation ratios and filter selection, data can be obtained from the AD7763 at four different data rates. The first filter receives data from the modulator at ICLK MHz, where it is decimated × ...
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... Following a SYNC , the digital filter needs time to settle before valid data can be read from the AD7763. The user knows there is valid data on the SDO line by checking the DVALID status bit (see D3 in the status bits listing) that is output with each conversion ...
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... SCO periods have elapsed, is ignored. Figure 3 also shows the format for the serial data written to the AD7763. A write operation requires 32 bits. The first 16 bits select the device and register address for which the data written is intended. The second 16 bits contain the data for the selected register ...
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... See the Downloading a User-Defined Filter section for further details. Writing to AD7763 is allowed at any time, even while reading a conversion result. Note that after writing to the devices, valid data is not output until after the settling time for the filter has elapsed ...
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... The WS and SCK signals that are used for the interface can be taken from either AD7763 device. Note that the device that is assigned Address 000 is defined as the left channel, and its data is output on the SD line when WS is logic low. ...
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... An internal clock signal (ICLK) is derived from the MCLK input signal. The ICLK controls the internal operations of the AD7763. The maximum ICLK frequency is 20 MHz, but due to an internal clock divider, a range of MCLK frequencies can be used. There ...
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... To obtain maximum performance from the AD7763 advisable to drive the ADC with differential signals. Figure 33 shows how a bipolar, single-ended signal biased around ground can drive the AD7763 with the use of an external op amp, such as the AD8021. With a 4.096 V reference supply must be provided to the reference buffer (AV ) ...
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... Downloading a User-Defined Filter). Values for gain, offset, and overrange threshold registers can also be written or read at this stage. BIAS RESISTOR SELECTION The AD7763 requires a resistor to be connected between the R pin and AGND. The value for this resistor is dependent on BIAS the reference voltage being applied to the device. The resistor value should be selected to give a current of 25 μ ...
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... AD7763 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7763, correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet. Figure 35 shows a simplified connection diagram for the AD7763. INA+ INA– OUTA– OUTA+ ...
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... EXPOSED PADDLE The AD7763 64-lead TQFP_EP employs × exposed paddle (see Figure 39). The paddle reduces the thermal resistance of the package by providing a path of low thermal resistance to the PCB and, in turn, increases the heat transfer efficiency from the AD7763 package ...
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... AD7763 PROGRAMMABLE FIR FILTER As discussed in the Theory of Operation section, the third FIR filter on the AD7763 can be programmed by the user. The default coefficients that are loaded on reset are shown in Table 12. This gives the frequency response shown in Figure 37. The frequencies shown in Figure 37 scale directly with the output data rate. ...
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... DOWNLOADING A USER-DEFINED FILTER As discussed in the Programmable FIR Filter section, each of the filter coefficients is 27 bits in length: one sign bit and 26 magni- tude bits. To download coefficients for a user-specific FIR filter, a 32-bit word is written to the AD7763 for each coefficient. D31 D30 D29 D28 ...
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... Address 000 (as assigned to the device using the ADR[2:0] pins). Table 16 lists in hexadecimal format the sequence of 32-bit Scaled words the user writes to the AD7763 to set up the ADC and +53188232 download this filter, assuming selection of an output data rate +29300796 of 625 kHz. ...
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... PD Power Down. Setting this bit powers down the AD7763, reducing the power consumption to 6.35 mW. 2 LPWR Low Power. If this bit is set, the AD7763 operates in a low power mode. The power consumption is reduced for reduction in noise performance must be written to this bit. ...
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... OVR If the current analog input exceeds the current overrange threshold, this bit is set. 7 DL_OK When downloading a user filter to the AD7763, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. 6 FILTER_OK When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter ...
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... Thin Quad Flat Package, Exposed Pad (TQFP_EP) Evaluation Board Rev Page 6.00 EXPOSED BSC SQ PAD BOTTOM VIEW (PINS UP 0.50 0.38 BSC 0.32 LEAD PITCH 0.22 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option SV-64-2 SV-64-2 AD7763 ...
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... AD7763 NOTES Rev Page ...
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... NOTES Rev Page AD7763 ...
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... AD7763 NOTES © 2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05476-0-11/09(A) Rev Page ...