AD9237 Analog Devices, AD9237 Datasheet - Page 19

• Manufacturer Part Number: AD9237
• Description: 12-Bit, 20/40/65 MSPS 3 V Low Power A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9237

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 65MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p,4 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 41 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes. When
multiple ADCs track one another, a single reference (internal or
external) reduces gain matching errors.
When the SENSE pin is connected to AVDD, the internal
reference is disabled, allowing the use of an external reference.
An internal reference buffer loads the external reference with
an equivalent 7 kΩ load. The internal buffer still generates the
positive and negative full-scale references, REFT and REFB, for
the ADC core. The input span is always four times the value of
the reference voltage divided by the span factor; therefore, the
external reference must be limited to a maximum of 1 V.
If the internal reference of the AD9237 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 42
shows how the internal reference voltage is affected by loading.
A 2 mA load is the maximum recommended load.
–0.05
–0.10
–0.15
–0.20
–0.25
0.05
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–40
0
–20
0.5
Figure 42. VREF Accuracy vs. Load
Figure 41. Typical VREF Drift
1.0
0
TEMPERATURE (°C)
1V ERROR (%)
1V REFERENCE
LOAD (mA)
0.5V REFERENCE
20
1.5
40
0.5V ERROR (%)
2.0
60
2.5
80
3.0
85
Rev. A | Page 19 of 24
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, can be
sensitive to clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9237 contains a clock
duty cycle stabilizer (DCS) that retimes the nonsampling, or
falling edge, providing an internal clock signal with a nominal
50% duty cycle. This allows a wide range of clock input duty
cycles without affecting the performance of the AD9237. As
shown in Figure 17, noise and distortion performance are
nearly flat over a 30% range of duty cycle with the DCS enabled.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
be calculated by
In this equation, the rms aperture jitter represents the root-
sum-square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in
cases where aperture jitter can affect the dynamic range of the
AD9237. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (such as gating, dividing, or other
methods), then it should be retimed by the original clock at the
last step.
The lowest typical conversion rate of the AD9237 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
POWER DISSIPATION, POWER SCALING, AND
STANDBY MODE
As shown in Figure 43, the power dissipated by the AD9237 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
where N is 12, the number of output bits.
SNR
I
DRVDD
Degradatio
=
V
DRVDD
INPUT
n
×
) due only to rms aperture jitter (t
=
C
20
LOAD
log
10
×
⎡
⎢
⎢
⎣
f
CLK
2
π
f
INPUT
×
1
N
t
J
⎤
⎥
⎥
⎦
AD9237
J
) can