AD7760 Analog Devices, AD7760 Datasheet - Page 2

• Manufacturer Part Number: AD7760
• Description: 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer
• Manufacturer: Analog Devices

Specifications of AD7760

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7760
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 18
Modulator Data Output Mode...................................................... 19
Modulator Data Output Mode Interface ..................................... 20
AD7760 Interface............................................................................ 22
Timing Specifications .................................................................. 6
Timing Diagrams.......................................................................... 7
ESD Caution.................................................................................. 8
Modulator Inputs........................................................................ 19
Modulator Data Output Scaling ............................................... 19
Clock Divide-by-1 Mode ( CDIV = 1) ..................................... 20
Clock Divide-by-2 Mode ( CDIV = 0) ..................................... 20
Using the AD7760 in Modulator Output Mode..................... 21
Reading Data............................................................................... 22
Reading Status and Other Registers......................................... 22
Sharing the Parallel Bus ............................................................. 22
Synchronization.......................................................................... 22
Rev. A | Page 2 of 36
Clocking the AD7760 .................................................................... 24
Driving the AD7760....................................................................... 26
Decoupling and Layout Recommendations................................ 28
Programmable FIR Filter............................................................... 30
Downloading a User-Defined Filter ............................................ 31
AD7760 Registers ........................................................................... 33
Outline Dimensions ....................................................................... 35
Writing to the AD7760 .............................................................. 23
Buffering the MCLK signal....................................................... 24
MCLK Jitter Requirements ....................................................... 24
Using the AD7760 ...................................................................... 27
Supply Decoupling ..................................................................... 29
Additional Decoupling .............................................................. 29
Reference Voltage Filtering ....................................................... 29
Differential Amplifier Components ........................................ 29
Bias Resistor Selection ............................................................... 29
Layout Considerations............................................................... 29
Exposed Paddle........................................................................... 29
Example Filter Download ......................................................... 31
Control Register 1—Address 0x0001 ...................................... 33
Control Register 2—Address 0x0002 ...................................... 33
Status Register (Read Only) ...................................................... 34
Offset Register—Address 0x0003............................................. 34
Gain Register—Address 0x0004............................................... 34
Overrange Register—Address 0x0005..................................... 34
Ordering Guide .......................................................................... 35