AD7939 Analog Devices, AD7939 Datasheet - Page 18

• Manufacturer Part Number: AD7939
• Description: 8-Channel, 1.5 MSPS, 10-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7939

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938/AD7939
CIRCUIT INFORMATION
The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit,
single-supply, successive approximation analog-to-digital
converters. The parts can operate from a 2.7 V to 5.25 V
power supply and feature throughput rates up to 1.5 MSPS.
The AD7938/AD7939 provide the user with an on-chip track-
and-hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP or
TQFP package.
The AD7938/AD7939 have eight analog input channels that
can be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo differential pairs, or seven pseudo
differential inputs with respect to one common input. There is
an on-chip user-programmable channel sequencer that allows
the user to select a sequence of channels through which the
ADC can progress and cycle with each consecutive falling edge
of CONVST .
The analog input range for the AD7938/AD7939 is 0 V to V
or 0 V to 2 × V
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938/AD7939 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0, in
the control register.
CONVERTER OPERATION
The AD7938/AD7939 are successive approximation ADCs
based around two capacitive digital-to-analog converters
(DACs). Figure 15 and Figure 16 show simplified schematics of
the ADC in acquisition and conversion phase, respectively. The
ADC comprises control logic, an SAR, and two capacitive DACs.
Both figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
V
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
IN−
V
V
IN+
IN–
is internally tied to AGND. In acquisition phase, SW3 is
B
A
A
B
V
REF
REF
SW1
SW2
, depending on the status of the RANGE bit in
Figure 15. ADC Acquisition Phase
C
C
S
S
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
REF
Rev. C | Page 18 of 36
When the ADC starts a conversion (Figure 16), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the V
otherwise, the two inputs have different settling times, resulting
in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7938/AD7939 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code
transitions occur at successive LSB values (1 LSB, 2 LSBs, and
V
of the AD7938/AD7939 for both straight binary and twos
complement output coding are shown in Figure 17 and Figure 18,
respectively.
so on) and the LSB size is V
REF
V
V
IN+
IN–
/1,024 for the AD7939. The ideal transfer characteristics
111...111
111...110
111...000
011...111
000...010
000...001
000...000
Figure 17. AD7938/AD7939 Ideal Transfer Characteristic
B
A
A
B
V
0V
REF
NOTES
1. V
SW1
SW2
with Straight Binary Output Coding
Figure 16. ADC Conversion Phase
REF
C
C
1 LSB
S
S
IS EITHER V
IN+
ANALOG INPUT
REF
SW3
REF
and the V
/4,096 for the AD7938 and
1 LSB = V
1 LSB = V
COMPARATOR
OR 2 × V
REF
REF
REF
IN−
/4096 (AD7938)
/1024 (AD7939)
.
pins must match;
+V
Data Sheet
REF
CAPACITIVE
CAPACITIVE
CONTROL
– 1 LSB
LOGIC
DAC
DAC