AD9289 Analog Devices, AD9289 Datasheet - Page 5

• Manufacturer Part Number: AD9289
• Description: Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9289

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
OUT-OF-RANGE RECOVERY TIME
1
TIMING DIAGRAMS
Actual valid time is dependent on the moment when LOCK goes low.
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO-to-Data Delay (t
DCO-to-FCO Delay (t
Data-to-Data Skew (t
PLL Lock Time (t
Wake-Up Time
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
F
R
) (20% to 80%)
) (20% to 80%)
V
)
1
LOCK
A
)
)
PD
FRAME
DATA-MAX
DCO–
DCO+
LOCK
DATA
CLK–
CLK+
FCO+
FCO–
D1+
)
D1–
AIN
EL
)
)
EH
FCO
STATIC
CPD
)
STATIC
)
)
– t
)
DATA-MIN
STATIC
)
N-1
t
A
t
V
t
t
FCO
PD
t
INVALID
CPD
t
EH
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
MSB
(N-7)
Figure 2. Timing Diagram
(N-7)
D6
Rev. 0 | Page 5 of 32
(N-7)
D5
t
EL
Test Level
VI
IV
VI
VI
IV
VI
V
V
V
V
VI
VI
IV
V
V
IV
V
V
V
(N-7)
D4
(N-7)
t
DATA
D3
N
(N-7)
D2
t
FRAME
(N-7)
D1
(N-7)
LSB
Min
65
6.9
6.9
0.5
6.9
MSB
(N-6)
Typ
7.7
7.7
9.0
250
250
9.0
9.0
±100
±100
±100
1.8
7
6
4.5
<1
1
STATIC
STATIC
STATIC
12
<1.5
11.6
±550
±500
±250
Max
CLK cycles
Unit
MSPS
MSPS
ns
ns
CLK cycles
ns
ps
ps
ns
ns
ps
ps
ps
µs
ms
CLK cycles
ns
ps rms
AD9289