AD7911 Analog Devices, AD7911 Datasheet
AD7911
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AD7911 Summary of contents
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... AD7911/AD7921 CONTROL LOGIC GND Figure 1. The AD7911/AD7921 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from V allowing the widest dynamic input range to the ADC. The analog input range for the part, therefore conversion rate is determined by the SCLK signal ...
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... AD7911/AD7921 TABLE OF CONTENTS Specifications..................................................................................... 3 AD7911 Specifications................................................................. 3 AD7921 Specifications................................................................. 5 Timing Specifications .................................................................. 7 Timing Diagrams.......................................................................... 7 Timing Examples.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Terminology .................................................................................... 11 Typical Performance Characteristics ........................................... 13 Circuit Information ........................................................................ 15 Converter Operation.................................................................. 15 ADC Transfer Function............................................................. 15 Typical Connection Diagram ................................................... 16 REVISION HISTORY 5/11—Rev Rev. A Updated Outline Dimensions ...
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... SPECIFICATIONS AD7911 SPECIFICATIONS Temperature range for A Grade from −40°C to +85° MHz SCLK SAMPLE Table 1. Parameter DYNAMIC PERFORMANCE Signal-to- Noise and Distortion (SINAD) 2 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) Second-Order Terms ...
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... AD7911/AD7921 Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) 4 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Operational from with V = 1.9 V minimum and V ...
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... DD 2 0.3 0 0.8 ±0.3 ±0.3 ±0 − 0.2 DD 0.2 ±0.3 5 Straight (natural) binary Rev Page AD7911/AD7921 Unit Test Conditions/Comments f = 100 kHz sine wave IN dB min dB typ dB min dB typ dB typ dB typ dB typ fa = 100.73 kHz 90.72 kHz dB typ fa = 100.73 kHz 90.72 kHz ns typ ps typ dB typ MHz typ ...
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... AD7911/AD7921 Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) 4 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Operational from with V = 1.9 V minimum and V ...
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... SCLK falling edge to DOUT three-state μs max Power-up time from full power-down OL SCLK 1.6V DOUT OH SCLK V IH DOUT V IL Rev Page AD7911/AD7921 or V voltage quoted in the timing characteristics is the true bus relinquish Figure 4. Hold Time after SCLK Falling Edge t 10 Figure 5 ...
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... AD7911/AD7921 TIMING EXAMPLES Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section. Timing Example 1 As shown in Figure 7, when MHz and the throughput is SCLK 250 kSPS, the cycle time 12.5(1 μs 2 SCLK ACQ With minimum, then t is 1.49 μ ...
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... Exposure to absolute −0 0.3 V maximum rating conditions for extended periods may affect DD 1 ±10 mA device reliability. −40°C to +85°C −65°C to +150°C 150°C 207°C/W 205.9°C/W 43.74°C/W 235 (0/+5)° Rev Page AD7911/AD7921 ...
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... DOUT Data Out. Logic output. The conversion result from the AD7911/AD7921 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK signal. For the AD7921, the data stream consists of two leading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to ...
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... TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7911/ AD7921, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ...
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... The AD7911/AD7921 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are ...
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... TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7921 and AD7911, respectively 250 kSPS sample rate and 100 kHz input frequency. Figure 12 shows the SINAD ratio performance versus the input frequency for various supply voltages while sampling at 250 kSPS with a SCLK frequency of 5 MHz for the AD7921 ...
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... AD7911/AD7921 1 2. 250kSPS SAMP TEMPERATURE = 25°C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE Figure 14. AD7921 INL Performance 1 2. 250kSPS 0.8 SAMP TEMPERATURE = 25°C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE Figure 15. AD7921 DNL Performance – ...
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... V IN0 V IN1 ADC TRANSFER FUNCTION The output coding of the AD7911/AD7921 is straight binary. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is V /4096 for the AD7921 and V DD ideal transfer characteristic for the AD7911/AD7921 is shown in Figure 21 ...
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... MSB of the 12-bit or 10-bit result. For the AD7911, the 10-bit result is followed by two trailing zeros. See the Serial Interface section. Alternatively, because the supply current required by the AD7911/AD7921 is so low, a precision reference can be used as the supply source to the AD7911/AD7921 ...
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... MSB provided first For the AD7911, the serial data stream consists of two leading DD zeros followed by the bit that identifies the channel converted, an invalid bit that matches up to the channel identifier bit, and the 10-bit conversion result with MSB provided first, followed + 0 ...
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... Figure 28 edge of SCLK, then the AD7911/AD7921 go back into power- down mode. This helps to avoid accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. Therefore, although the device might begin to ...
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... CHANNEL FOR NEXT CONVERSION DOUT INVALID DATA POWER-UP TIME The power-up time of the AD7911/AD7921 is 1 μs, which means that with any frequency of SCLK MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly ...
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... V, SCLK= 5 MHz, and the device is again in power- DD down mode between conversions, then the power dissipation during normal operation is 6 mW. The AD7911/AD7921 now dissipate 6 mW for 6.4 μs during each conversion cycle. With a throughput rate of 50 kSPS, the average power dissipated during each cycle is (6.4/20) × ...
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... Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7921. For the AD7911, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track- and-hold goes back into track on the next SCLK rising edge, as shown in Figure 31 at Point B ...
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... For the AD7921, the word length should be set to 16 bits ( the SPC register). This DSP allows frames with a word length of 16 bits or 8 bits only. In the AD7911, therefore, where 14 bits are required, the FO bit should be set bits, and 16 SCLKs are needed. For the AD7911, two trailing zeros are clocked out in the last two clock cycles ...
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... Register A (CRA setting Bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7921. This DSP does not offer the option for a 14-bit word length, so the AD7911 word length is set bits like the AD7921. For the AD7911, the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word ...
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... A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7911/ AD7921 system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7911/AD7921 ...
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... AD7911ARMZ-REEL −40°C to +85°C AD7911ARM-REEL7 −40°C to +85°C AD7911ARMZ-REEL7 −40°C to +85°C AD7911AUJZ-R2 −40°C to +85°C AD7911AUJZ-REEL7 −40°C to +85°C AD7921ARMZ −40°C to +85°C AD7921ARMZ-REEL −40°C to +85°C AD7921ARMZ-REEL7 −40°C to +85°C AD7921AUJZ-R2 − ...
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... AD7911/AD7921 NOTES Rev Page ...
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... NOTES Rev Page AD7911/AD7921 ...
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... AD7911/AD7921 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04350–0–5/11(A) Rev Page ...