AD7912 Analog Devices, AD7912 Datasheet
AD7912
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AD7912 Summary of contents
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... AD7912/AD7922 CONTROL LOGIC GND Figure 1. Several AD7912/AD7922 can be connected together in a daisy chain. The AD7912/AD7922 feature a daisy-chain mode that allows the user to read the conversion results from the ADCs contained in the chain. The AD7912/AD7922 use advanced design techniques to achieve very low power dissipation at high throughput rates ...
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... Revision 0: Initial Version DIN Input.................................................................................... 17 DOUT Output ............................................................................ 17 Modes of Operation ....................................................................... 18 Normal Mode.............................................................................. 18 Power-Down Mode.................................................................... 18 Power-Up Time .......................................................................... 20 Daisy-Chain Mode ..................................................................... 20 Daisy-Chain Example ................................................................ 22 Power vs. Throughput Rate ........................................................... 24 Serial Interface ................................................................................ 25 Microprocessor Interfacing....................................................... 26 Application Hints ........................................................................... 28 Grounding and Layout .............................................................. 28 Evaluating AD7912/AD7922 Performance................................. 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30 Rev Page ...
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... SPECIFICATIONS AD7912 SPECIFICATIONS Temperature range for A Grade from −40°C to +85° MHz SCLK Table 1. Parameter DYNAMIC PERFORMANCE Signal-to- Noise + Distortion (SINAD Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) Second-Order Terms ...
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... AD7912/AD7922 Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) 4 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Operational from with V = 1.9 V minimum and V ...
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... V DD ±0 0.3 0 0.8 ±0.3 ±0.3 ±0.3 5 Rev Page AD7912/AD7922 Unit Test Conditions/Comments f = 100 kHz sine wave IN dB min dB typ dB min dB typ dB typ dB typ dB typ fa = 100.73 kHz 90.72 kHz dB typ fa = 100.73 kHz 90.72 kHz ns typ ps typ dB typ MHz typ ...
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... AD7912/AD7922 Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance 3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time 2 Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) ...
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... SCLK falling edge to DOUT three-state Power-up time from full power-down OL SCLK 1.6V DOUT OH SCLK V IH DOUT V IL Rev Page AD7912/AD7922 or V voltage quoted in the timing characteristics is the true bus relinquish Figure 4. Hold Time after SCLK Falling Edge ...
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... AD7912/AD7922 TIMING EXAMPLES Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section. Timing Example 1 As shown in Figure 7, when MHz and the throughput SCLK is 1 MSPS, the cycle time 12.5(1 µs 2 SCLK ACQ With minimum, then t ...
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... Exposure to absolute −0 0.3 V maximum rating conditions for extended periods may affect DD 1 ±10 mA device reliability. −40°C to +85°C −65°C to +150°C 150°C 207°C/W 205.9°C/W 43.74°C/W 235 (0/+5)°C 1.5 kV Rev Page AD7912/AD7922 ...
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... MSB first. For the AD7912, the data stream consists of two leading zeros, the channel identifier bit that identifies which channel the conversion result corresponds to, followed by the mode bit that indicates the current mode of operation, followed by the 10 bits of conversion data with MSB first and two trailing zeros ...
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... TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7912/ AD7922, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ...
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... The AD7912/AD7922 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are ...
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... TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7922 and AD7912, respectively MSPS sample rate and 100 kHz input frequency. Figure 12 shows the SINAD performance versus the input frequency for various supply voltages while sampling at 1 MSPS with a SCLK frequency of 18 MHz for the AD7922 ...
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... AD7912/AD7922 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE Figure 14. AD7922 INL Performance 1 0.8 TEMPERATURE = 25 ° C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE Figure 15. AD7922 DNL Performance –20 –30 – 1kΩ IN –50 – ...
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... The AD7912/AD7922 feature a power-down option that allows power saving between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. The AD7912/AD7922 can also be used in daisy-chain mode when several AD7912/AD7922 are connected in a daisy chain. This mode of operation is selected by controlling the logic state of the CS signal ...
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... (for example, 15 V). The REF19x outputs a steady voltage to the AD7912/AD7922. If the low dropout REF193 is used, the current it needs to supply to the AD7912/ AD7922 is typically1.5 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 needs to supply a maximum the AD7912/AD7922 ...
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... See the Daisy-Chain Mode section for more details the AD7912/AD7922 are not going to be used in daisy-chain mode recommended to keep STY and CHN the same (STY = CHN). In that case, the channel can be selected by tying DIN either high or low during a conversion cycle. ...
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... For the AD7922, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7912, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. ...
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... Figure 27. Entering Daisy-Chain Mode 10 THREE-STATE INVALID DATA THREE-STATE INVALID DATA Figure 28. Entering Power- Down Mode THE PART IS FULLY POWERED UP WITH V FULLY ACQUIRED CHANNEL FOR NEXT CONVERSION CONVERSION RESULT Figure 29. Exiting Power-Down Mode Rev Page AD7912/AD7922 AD7912/AD7922 NORMAL MODE 16 ...
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... CS high after the 10th falling edge of SCLK and before the 12th falling edge of SCLK, as shown in Figure 27. To ensure that the AD7912/AD7922 are placed into daisy-chain mode, CS should not be brought high until at least 20 ns after the 10th SCLK falling edge and before the fully. 1 µ ...
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... DOUT:CHN MOD *CS HIGH BETWEEN THE 10TH–12TH SCLK POWER-UP TIME AND CS HIGH AFTER THE 13TH SCLK CS HIGH BETWEEN THE 2ND–10TH SCLK POWER-DOWN MODE Rev Page AD7912/AD7922 NORMAL MODE NORMAL MODE 16 CONVERSION CYCLE ≠ DIN: CHN STY ...
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... Figure more detailed diagram that shows the data presented on the DIN pin and clocked out on the DOUT pin for each of the AD7912/AD7922 in Figure 33. If the DOUT1 (or DIN2) signal is ignored, Figure 35 brings about Figure 34. ...
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... CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1 COMMAND2 SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2 COMMAND3 Figure 35. Daisy-Chain Diagrams—II Rev Page AD7912/AD7922 CHANGE MODE CS HIGH BETWEEN THE NORMAL MODE CONVERSION ON THE 10TH–13TH SCLK TWO DEVICES ...
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... DD time is one dummy cycle (1 µs), and the remaining conversion time is another cycle (1 µs), then the AD7912/AD7922 dissipate 20 mW for 2 µs during each conversion cycle. If the throughput rate is 100 kSPS and the cycle time is 10 µs, then the average power dissipated during each cycle is (2/10) × ...
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... Figure 37. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7922. For the AD7912, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track- and-hold goes back into track on the next SCLK rising edge, as shown in Figure 38 at Point B ...
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... AD7922, the word length should be set to 16 bits ( the SPC register). This DSP allows frames with a word length of 16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are required, the FO bit should be set bits, and 16 SCLKs are needed. For the AD7912, two trailing zeros are clocked out in the last two clock cycles ...
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... Register A (CRA setting bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7922. This DSP does not offer the option for a 14-bit word length, so the AD7912 word length is set bits like the AD7922. For the AD7912, the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word ...
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... A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7912/ AD7922 are in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7912/AD7922 ...
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... AD7912/AD7922. The software allows the user to perform ac (Fast Fourier Transform) and dc (histograms of codes) tests on the AD7912/AD7922. See the AD7912/AD7922 Technical Note for more information. The technical note is included in the software, and it can also be found on the www.analog.com link on the AD7912/AD7922 product page. ...
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... AD7912ARM −40°C to +85°C AD7912ARM-REEL −40°C to +85°C AD7912ARM-REEL7 −40°C to +85°C AD7912AUJ-R2 −40°C to +85°C AD7912AUJ-REEL7 −40°C to +85°C AD7922ARM −40°C to +85°C AD7922ARM-REEL −40°C to +85°C AD7922ARM-REEL7 −40°C to +85°C AD7922AUJ-R2 − ...
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... NOTES Rev Page AD7912/AD7922 ...
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... AD7912/AD7922 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04351–0–4/04(0) Rev Page ...