AD7451 Analog Devices, AD7451 Datasheet - Page 13

• Manufacturer Part Number: AD7451
• Description: Pseudo Differential Input, 1 MSPS, 12-Bit ADC in an 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7451

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7441/AD7451 are 10-/12-bit, high speed, low power,
single-supply, successive approximation, analog-to-digital con-
verters (ADCs) with a pseudo differential analog input. These
parts operate with a single 2.7 V to 5.25 V power supply and are
capable of throughput rates up to 1 MSPS when supplied with
an 18 MHz SCLK. The AD7441/AD7451 require an external
reference to be applied to the V
The AD7441/AD7451 have a SAR ADC, an on-chip differential
track-and-hold amplifier, and a serial interface housed in either
an 8-lead SOT-23 or an MSOP package. The serial clock input
accesses data from the part and provides the clock source for
the SAR ADC. The AD7441/AD7451 feature a power-down
option for reduced power consumption between conversions.
The power-down feature is implemented across the standard
serial interface, as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7441/AD7451 are SAR ADCs based around two
capacitive DACs. Figure 19 and Figure 20 show simplified
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 19 (acquisition phase), SW3
is closed, SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
V
V
IN+
IN–
B
A
A
B
V
REF
SW1
SW2
Figure 19. ADC Acquisition Phase
C
C
S
S
SW3
REF
COMPARATOR
pin.
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
Rev. D | Page 13 of 24
When the ADC starts a conversion (see Figure 20), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. The output impedances of the sources
driving the V
two inputs have different settling times, resulting in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7441/AD7451 is straight (natural)
binary. The designed code transitions occur at successive LSB
values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451
is V
ideal transfer characteristic of the AD7441/AD7451 is shown in
Figure 21.
V
V
IN+
IN–
REF
/4096, and the LSB size of the AD7441 is V
Figure 21. AD7441/AD7451 Ideal Transfer Characteristic
B
A
A
B
111...111
111...110
111...000
011...111
000...010
000...001
000...000
IN+
V
REF
SW1
SW2
and V
Figure 20. ADC Conversion Phase
0V
C
C
S
S
1LSB
1LSB = V
1LSB = V
IN–
pins must be matched; otherwise the
SW3
REF
REF
ANALOG INPUT
/4096 (AD7451)
/1024 (AD7441)
COMPARATOR
AD7441/AD7451
V
REF
– 1LSB
CAPACITIVE
CAPACITIVE
REF
CONTROL
LOGIC
DAC
DAC
/1024. The