AD7451 Analog Devices, AD7451 Datasheet - Page 7

• Manufacturer Part Number: AD7451
• Description: Pseudo Differential Input, 1 MSPS, 12-Bit ADC in an 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7451

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
TIMING DIAGRAMS
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Guaranteed by characterization. All input signals are specified with t
and the Serial Interface section.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
cross 0.4 V or 2.0 V for V
t
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t
time of the part and is independent of the bus loading.
See the Power-Up Time section.
3
4
8
DD
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
2
= 2.7 V to 5.25 V; f
5
Limit at T
10
18
16 × t
888
60
10
10
20
40
0.4 t
0.4 t
10
10
35
1
SDATA
SDATA
SCLK
SCLK
CS
SCLK
SCLK
CS
SCLK
DD
= 3 V.
t
t
SCLK
t
t
2
3
MIN
2
3
, T
= 18 MHz; f
MAX
0
0
1
1
1
4 LEADING ZEROS
4 LEADING ZEROS
0
0
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
2
2
S
= 1 MSPS; V
0
0
3
3
t
t
Figure 2. AD7451 Serial Interface Timing Diagram
Figure 3. AD7441 Serial Interface Timing Diagram
4
4
0
0
Description
t
Minimum quiet time between end of a serial read and next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA, three-state enabled
SCLK falling edge to SDATA, three-state enabled
Power-up time from full power-down
SCLK
REF
4
4
DB11
= 1/f
DB9
= 2.5 V; T
RISE
t
t
5
5
= t
SCLK
Rev. D | Page 7 of 24
FALL
5
5
t
t
DB10
7
7
DB8
t
t
= 5 ns (10% to 90% of V
CONVERT
CONVERT
A
= T
MIN
to T
13
13
B
B
MAX
DB0
DB2
, unless otherwise noted.
DD
8
14
14
t
) quoted in the timing characteristics is the true bus relinquish
t
2 TRAILING ZEROS THREE-STATE
6
6
) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,
DB1
0
15
15
t
t
DB0
8
8
0
DD
= 5 V and the time required for an output to
16
16
THREE-STATE
t
t
QUIET
QUIET
t
t
AD7441/AD7451
1
1