AD9865 Analog Devices, AD9865 Datasheet
AD9865
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AD9865 Summary of contents
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... APPLICATIONS Powerline networking VDSL and HPNA GENERAL DESCRIPTION The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital inter- ...
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... AD9865 TABLE OF CONTENTS Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications ....................................................... 5 Digital Specifications ................................................................... 6 Serial Port Timing Specifications............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 7 Full-Duplex Data Interface (Tx and Rx Port) Timing Specifications ................................................................................ 8 Explanation of Test Levels........................................................... 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution ...
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... Monotonic ±2 0.5 62.0 63.1 62.5 63.2 −77.7 −67.0 67.1 79.3 2 105 2 150 43.3 45.2 −19.5 0 0.5 Monotonic 0.5 1.23 0.7 3 0.2187 0.2405 50 AD9865 Unit Bits MSPS µ dBm dBc dBc dBc dBc dBm dBc ppm/ C Cycles f /f OUT DAC f /f OUT ...
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... AD9865 Parameter Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative DAC −0.2 dB Bandwidth −3 dB Bandwidth Stop Band Rejection (0.289 f to 0.711 f OSCIN PLL CLK MULTIPLIER OSCIN Frequency Range Internal VCO Frequency Range Duty Cycle OSCIN Impedance 5 CLKOUT1 Jitter 6 CLKOUT2 Jitter 7 CLKOUT1 and CLKOUT2 Duty Cycle 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 ...
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... DATA Test Level Min Typ Max V 3.135 3.3 3.465 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3.3 3.6 II 406 475 IV 311 342 IV 95 133 AD9865 Unit Cycles Cycles dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Unit ...
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... AD9865 Parameter POWER CONSUMPTION (Half-Duplex Operation with f Tx Mode AVDD CLKVDD DVDD DRVDD Rx Mode AVDD CLKVDD DVDD DRVDD POWER CONSUMPTION OF FUNCTIONAL BLOCKS RxPGA and LPF ADC TxDAC IAMP (Programmable) Reference CLK PLL and Synthesizer MAXIMUM ALLOWABLE POWER DISSIPATION ...
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... Test Level Min Typ Max 1 2 AD9865 Unit MHz MHz Unit MSPS MSPS MSPS MSPS ...
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... AD9865 FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Tx PATH INTERFACE (See Figure 53) Input Nibble Rate (2× Interpolation) Input Nibble Rate (4× Interpolation) Tx Data Setup Time ( Data Hold Time ( ...
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... Thermal Resistance: 64-lead LFCSP (4-layer board). −0 DRVDD + 0.3 V θ = 24°C/W (paddle soldered to ground plane, 0 LPM air maximum JA θ = 30.8°C/W (paddle not soldered to ground plane, JA −40°C to +85°C 0 LPM air). 125°C 150°C −65°C to +150°C Rev Page AD9865 ...
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... NC Rx[ Rx[0] 13 RXEN RXSYNC 14 TXEN TXSYNC PIN 1 3 IDENTIFIER AD9865 7 TOP VIEW 8 (Not to Scale Figure 2. Pin Configuration 1 Mode Description HD MSB of ADIO Buffer FD MSB of Tx Nibble Input ...
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... LOW = HD, HIGH = FD Power-Up SPI Register Default Setting Input Clock Oscillator/Synthesizer Supply Return Crystal Oscillator Inverter Output Crystal Oscillator Inverter Input Clock Oscillator/Synthesizer Supply Digital Supply Return Digital Supply Input f /L Clock Output OSCIN Power-Down Input Rev Page AD9865 ADC ...
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... AD9865 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 FUND = –1dBFS 0 SINAD = 59.1dBFS ENOB = 9.53 BITS –10 SNR = 60.2dBFS THD = –65.2dBFS –20 SFDR = –64.9dBc (THIRD HARMONIC) RBW = 12.21kHz – ...
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... RxPGA GAIN (dB) Figure 13. THD vs. RxPGA Gain and Frequency SINAD @ +25°C SINAD @ +85°C SINAD @ –40°C THD @ +25°C THD @ +85°C THD @ –40°C – RxPGA GAIN (dB MHz) IN AD9865 10.0 5MHz 10MHz 15MHz 9.5 20MHz 30MHz 9.0 8.5 8.0 7.5 7.0 6 5MHz 10MHz 15MHz 20MHz ...
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... CUTOFF FREQUENCY (MHz) Figure 19. SNR vs. Filter Cutoff Frequency = 5 MHz; AIN = −1 dB; RxPGA = 48 dB) (50 MSPS 0.5 0.4 0.3 0.2 0.1 0 AD9865: GAIN STEP ERROR @ +25 ° C AD9865: GAIN STEP ERROR @ +85 ° C AD9865: GAIN STEP ERROR @ –40 ° C – RxPGA GAIN (dB) Figure 20. RxPGA Gain Step Error vs. Gain (f IN – ...
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... INPUT FREQUENCY (MHz) (LPF MHz) − FREQUENCY (MHz) Figure 26. Rx Input Impedance vs. Frequency AD9865 640 720 –6dB GAIN 0dB GAIN +6dB GAIN 105 ...
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... AD9865 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 (see Figure 63) into 50 Ω load half- or full-duplex interface, default power bias settings –10 –20 –30 –40 –50 –60 –70 – FREQUENCY (MHz) Figure 27. Dual-Tone Spectral Plot of TxDAC's Output ( MSPS, 4× ...
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... FREQUENCY (MHz MSPS, 2× Interpolation) DATA 2-TONE IMD SNR –24 –21 –18 –15 –12 –9 –6 AOUT (dBFS) Figure 38. SNR and SFDR vs. P OUT ( MHz MSPS, 2× Interpolation) OUT DATA AD9865 35 40 140 160 –3 0 ...
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... AD9865 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 – FREQUENCY (MHz) Figure 39. Dual-Tone Spectral Plot of IAMPN Output (IAMP Settings 12.5 mA 2:1 Transformer into 75 Ω ...
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... Rev Page AD9865 Comments CONFIG = 1 0 Default SPI configuration is 3-wire, MSB first PWR_DWN = 0. Default setting is for all 0 blocks powered on PWR_DWN = 1. Default setting* is for all 1 ...
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... AD9865 Bit Address Break- 1 (Hex) down Description 0x08 (7:0) Rx Filter Tuning Cut-off Frequency Tx/Rx PATH GAIN CONTROL 0x09 (6) Use SPI Rx Gain (5:0) Rx Gain Code 0x0A (6) Use SPI Tx Gain (5:0) Tx Gain Code Tx AND Rx PGA CONTROL 0x0B (6) PGA Code for Tx (5) PGA Code for Rx (3) Force GAIN strobe ...
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... Tx path and RxPGA gain mapping. SERIAL PORT INTERFACE (SPI) The serial port of the AD9865 has 3- or 4-wire SPI capability allowing read/write access to all registers that configure the device’s internal parameters. Registers pertaining to the SPI are listed in Table 11 ...
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... LSB first. Multibyte data trans- fers in LSB format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. The AD9865 automatically increments the address for each successive byte required for the multibyte communication cycle. ...
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... The half-duplex interface can be configured to act as a slave DIS master to the digital ASIC. An example of a slave configuration is shown in Figure 51. In this example, the AD9865 accepts all TX3 TX4 the clock and control signals from the digital ASIC. Because the sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must be at exactly the same frequency as the OSCIN signal ...
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... A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9865 to be completely powered down (including the clock synthesizer) while serving as the master. ...
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... Rx Data[5:0] RX_SYNC TX_SYNC RxPGA CONTROL The AD9865 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over − +48 dB with 1 dB resolution using a 6-bit word, and with setting corresponding p-p input signal. ...
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... AD9865 –6 – 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT Figure 56. Digital Gain Mapping of RxPGA Table 15. SPI Registers RxPGA Control Address (Hex) Bit Description 0x09 (6) Enable RxPGA update via SPI (5:0) RxPGA gain code 0x0B (6) Select TxPGA via PGA[5:0] ...
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... TXPGA CONTROL The AD9865 also contains a digital PGA in the Tx path distri- buted between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A 6-bit word is used to set the TxPGA attenuation according to the mapping shown in Figure 58 ...
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... AD9865 TRANSMIT PATH The AD9865 (or AD9866) transmit path consists of a selectable digital 2×/4× interpolation filter, a 10-bit or 12-bit TxDAC, and a current-output amplifier (IAMP) as shown in Figure 59. Note that the additional two bits of resolution offered by the AD9866 result reduction in the pass-band noise floor ...
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... Most applications can disable these current sources (set via Register 0x12) to reduce the IAMP’s current consumption. Rev Page from the TxDAC are S 2 × × I and I OFF1 OFF2 AD9865 via Register 0x12 ...
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... AD9865 Table 19. SPI Registers for TxDAC and IAMP Address (Hex) Bit Description 0x0E (0) TxDAC output 0x10 (7) Enable current mirror gain settings (6:4) Secondary path first stage gain with ∆ (3) Not used (2:0) Primary path NMOS gain with ∆ ...
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... VOUT × I × {(AVDD − VOUT ) × N IAMP PK − 0.65) × via a 0.1 µF blocking capacitor and series resistor of 1 Ω , and add margin to ensure that the npn PK AD9865 R 0.1µ LOAD R 0.1µF S (4) − 0.65 (5) ...
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... This feature is advantageous in half-duplex applications (for example, power lines) in which the Tx output driver must go into a high impedance state while in Rx mode. If the AD9865 is configured for the half-duplex mode (MODE = 0), the IAMP, TxDAC, and interpolation filter are automatically powered ...
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... RECEIVE PATH The receive path block diagram for the AD9865 (or AD9866) is shown in Figure 68. The receive signal path consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) ADC. Note that the additional two bits of resolution offered by the AD9866 result lower noise floor depending on the RxPGA gain setting and LPF cutoff frequency ...
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... AD9865 LOW-PASS FILTER The low-pass filter (LPF) provides a third order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span. Figure 68 shows that the first real pole is im- plemented within the first CPGA gain stage, and the complex pole pair is implemented in the second CPGA gain stage ...
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... Bit 4 of Register 0x07. Alternative power bias settings are also available via Register 0x13, as discussed in the Power Control and Dissipation section. Lastly, the ADC can be completely powered down for half-duplex operation, further reducing the AD9865’s peak power consumption. 192 208 ...
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... AD9865 REFT TO ADCs REFB 1.0V TOP VIEW C1 C4 Figure 75. ADC Reference and Decoupling The ADC has an internal voltage reference and reference ampli- fier as shown in Figure 75. The internal band gap reference generates a stable 1 V reference level that is converted to a dif- ferential 1 V reference centered about mid-supply (AVDD/2). ...
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... DATA OSCIN Note: if the reference frequency appearing at OSCIN is chosen to be equal to the AD9865’s Tx and Rx path’s word rate, then M is simply equal to log (F). 2 The clock source for the ADC can be selected in Register 0x04 as a buffered version of the reference frequency appearing at ...
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... AD9865 at OSCIN (or RXCLK) can be determined upon power up. Also, this clock has near 50% duty cycle, because it is derived from the VCO result, CLKOUT1 should be selected before CLKOUT2 as the primary source for system clock distribution. CLKOUT2 is a divided version of the reference frequency, f and can be set submultiple integer of f where ...
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... In the case of a full-duplex digital interface (MODE = 1), one can set Register 0x01 to 0x60 and Register 0x02 to Register 0x05 (or vice versa) such that the AD9865’s Tx and Rx path are never powered on simultaneously. The PWRDWN pin can then be used to control which path is powered on, depending on the burst type. During a Tx burst, the Rx path’ ...
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... To disable the fast power-down of the Tx and/or Rx circuitry, set Bit 1 and/or Bit POWER REDUCTION OPTIONS The power consumption of the AD9865 can be significantly reduced from its default setting by optimizing the power consumption versus performance of the various functional blocks in the Tx and Rx signal path. On the Tx path, minimum power consumption is realized when the TxDAC output is used directly and its standing current reduced to as low ...
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... THD-00 THD-01 53 THD-10 THD- SAMPLE RATE (MSPS) and SPGA Bias Setting with ADC = 10 MHz, LPF set to 26 MHz, and AIN = −1 dBFS IN AD9865 70 80 –54 –56 –58 SNR-00 –60 SNR-01 SNR-10 –62 SNR-11 –64 –66 –68 –70 –72 – ...
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... AD9875. Other applications must use the SPI to configure the device. A hardware ( RESET pin) or software (Bit 5 of Register 0x00) reset can be used to place the AD9865 into a known state of operation as determined by the state of the MODE and CONFIG pins offset calibration and filter tuning routine is also initiated upon a hardware reset, but not with a software reset ...
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... ADC. Digital loop-back can be used to test the full-duplex digital interface of the AD9865. In this test, data appearing on the Tx[5:0] port is routed back to the Rx[5:0] port, thereby confirming proper bus operation. The Rx port can also be three-stated for half- and full-duplex interfaces ...
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... MxFE. The AD9865 has several pins that are used to decouple sensitive internal nodes. These pins are REFIO, REFB, and REFT. The decoupling capacitors connected to these points should have low ESR and ESL ...
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... MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the MxFE further reduces the possibility of noise corrupting these signals. Rev Page AD9865 ...
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... AD9865 EVALUATION BOARD An evaluation board is available for the AD9865 and AD9866. The digital interface to the evaluation board can be configured for a half- or full-duplex interface. Two 40-pin and one 26-pin male right angle headers (0.100 inches) provide easy interfacing to test equipment such as digital data capture boards, pattern generators, or custom digital evaluation boards (FPGA, DSP, or ASIC) ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range AD9865BCP −40°C to +85°C AD9865BCPRL −40°C to +85°C AD9865BCPZ 1 −40°C to +85°C 1 AD9865BCPZRL −40°C to +85°C AD9865CHIPS AD9865- Pb-free part. 9.00 BSC SQ 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.45 0. 0.35 0.80 MAX 0.65 TYP ...
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... AD9865 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04493–0–11/04(A) Rev Page ...