AD7655 Analog Devices, AD7655 Datasheet
AD7655
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AD7655 Summary of contents
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... Fast Throughput. The AD7655 MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 3. Single-Supply Operation. The AD7655 operates from a single 5 V supply. In impulse mode, its power dissipation decreases with throughput. 4. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangements are compatible with both 3 V and 5 V logic ...
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... Serial Interface ............................................................................ 20 Master Serial Interface............................................................... 20 Slave Serial Interface .................................................................. 22 Microprocessor Interfacing....................................................... 24 SPI Interface (ADSP-219 Application Hints ........................................................................... 25 Layout .......................................................................................... 25 Evaluating the AD7655 Performance ...................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 12/04—Rev Rev. A Changes to Figure 17...................................................................... 15 Changes to Figure 18...................................................................... 16 Changes to Voltage Reference Input section .............................. 17 Changes to Conversion Control section ..................................... 18 Changes to Digital Interface section ...
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... 100 kHz IN Full-scale step 2.3 1 MSPS throughput −0.3 +2.0 −1 − 1.6 mA SINK I = −500 μA OVDD − 0.2 SOURCE Rev Page AD7655 , unless otherwise noted. MAX Typ Max Unit Bits REF +0 μA 2 μs 1 MSPS 2.25 μs ...
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... AD7655 Parameter POWER SUPPLIES Specified Performance AVDD DVDD OVDD 9 Operating Current AVDD DVDD OVDD Power Dissipation 11 TEMPERATURE RANGE Specified Performance 1 See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. 3 LSB means least significant bit. With the input range, 1 LSB is 76.294 μV. ...
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... Rev Page AD7655 , unless otherwise noted. MAX Min Typ Max 5 2/2.25 32 1.75 1.75/2 250 10 30 1/1.25 45 0.75 250 30 1.75 250/500 ...
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... AD7655 Parameter SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load serial master read during convert mode ...
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... JA = 26°C/ DELAY Rev Page 1.6mA OL TO OUTPUT 1.4V PIN C L 60pF* I 500μ 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing 2V 0.8V t DELAY 2V 2V 0.8V 0.8V Figure 3. Voltage Reference Levels for Timing AD7655 ...
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... When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW AGND 1 PIN 1 AVDD BYTESWAP 4 A/B 5 AD7655 DGND 6 TOP VIEW (Not to Scale) IMPULSE 7 SER/PAR D2/DIVSCLK[0] ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input ...
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... AD7655 1 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition phase (t immediately started. 37 REF AI This input pin is used to provide a reference to the converter. ...
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... Aperture delay is a measure of acquisition performance and is measured from the falling edge of the CNVST input to when the input signals are held for a conversion. Transient Response The time required for the AD7655 to achieve its rated accuracy after a full-scale step function is applied to its input. Rev Page AD7655 ...
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... AD7655 TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 32768 0 16384 CODE Figure 5. Integral Nonlinearity vs. Code 8000 7059 6894 7000 6000 5000 4000 3000 2000 1230 1094 1000 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 CODE IN HEX Figure 6 ...
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... Rev Page NORMAL AVDD IMPULSE AVDD IMPULSE DVDD OVDD 2.7V 10 100 SAMPLING RATE (kSPS) Figure 14. Operating Currents vs. Sample Rate OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 50 100 150 C (pF) L Figure 15. Typical Delay vs. Load Capacitance C AD7655 1000 200 L ...
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... The AD7655 can also be used as a 4-channel ADC with two pairs simultaneously sampled. The AD7655 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP or a tiny, 48-lead LFCSP that combines space savings and allows flexible configurations as either a serial or parallel interface ...
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... DVDD OVDD REF REF A NOTE 1 REF B REFGND INA1 AD7655 INA2 INAN INB1 INB2 INBN IS 47μF. SEE VOLTAGE REFERENCE INPUT SECTION. REF Rev Page AD7655 DIGITAL SUPPLY (3.3V OR 5V) + 100nF 10μF OGND SERIAL PORT SCLK SDOUT BUSY μC/μP/ 50Ω DSP CNVST D ...
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... This one-pole filter with a typical −3 dB cutoff frequency of 10 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs. Because the input impedance of the AD7655 is very high, the AD7655 can be driven directly by a low impedance source without gain error. To further improve the noise filtering of the ...
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... Figure 20. This feature makes the AD7655 ideal for very low power battery applications. Note that the digital interface remains active even during the acquisition phase ...
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... The serial interface is multiplexed on the parallel data bus. The AD7655 digital interface accommodates either logic when the OVDD supply pin of the AD7655 is connected to the host system interface digital supply. The two signals, CS and RD , control the interface. When at least one of these signals is high, the interface outputs are in high impedance ...
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... However, in any of the serial reading modes Channel A data is updated only after Channel B conversion. DATA BUS Rev Page HI-Z HIGH BYTE LOW BYTE HI-Z LOW BYTE HIGH BYTE Figure 26. 8-Bit Parallel Interface CS RD A/B HI-Z CHANNEL A CHANNEL Figure 27 Channel Reading AD7655 HI HI-Z HI-Z ...
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... AD7655 SERIAL INTERFACE The AD7655 is configured to use the serial interface when the SER/ PAR is held high. The AD7655 outputs 32 bits of data, MSB first, on the SDOUT pin. The order of the channels being output is also controlled When high, Channel A is output first; ...
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... D14 D0 D15 D15 INVSCLK = INVSYNC = 0 RDC/SDIN = D15 D14 Rev Page AD7655 A A ...
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... Figure 31 and Figure 32 show the detailed timing diagrams of these methods. While the AD7655 is performing a bit decision important that voltage transients do not occur on digital input/output pins or degradation of the conversion result could occur. This is ...
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... Figure 32. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) INVSCLK = D13 D13 D1 D0 INVSCLK = D13 Rev Page AD7655 A D15 D14 D15 D14 A ...
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... Figure 33 shows an interface diagram between the AD7655 and the SPI1-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7655 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature to be used. The convert command can be initiated in response to an internal timer interrupt ...
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... Additionally, low ESR 10 μF capacitors should be located near the ADC to further reduce low frequency ripple. The DVDD supply of the AD7655 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when ...
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... AD7655 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 ROTATED 90° CCW BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° SEATING 0.08 MAX PLANE VIEW A 0.50 COPLANARITY BSC LEAD PITCH VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7 ...
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... AD7655ACPZ −40°C to +85°C 1 AD7655ACPZRL −40°C to +85°C AD7655AST −40°C to +85°C AD7655ASTRL −40°C to +85°C 1 AD7655ASTZ −40°C to +85°C AD7655ASTZRL 1 −40°C to +85°C 2 EVAL-AD7655CB 3 EVAL-CONTROL-BRD3 Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD3 for evaluation/demonstration purposes. ...
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... AD7655 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03536-0-9/05(B) T Rev Page ...